Zsolt Tokei

Person

Leuven, BE

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with an interconnection system having a multilev...
- Patent number 11,342,261
- Issue date May 24, 2022
- Imec VZW
- Stefan Cosemans
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a via hole self-aligned with a metal block on a...
- Patent number 11,270,912
- Issue date Mar 8, 2022
- Imec VZW
- Martin O'Toole
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor fabrication method for producing nano-scaled electric...
- Patent number 11,264,271
- Issue date Mar 1, 2022
- Imec VZW
- Martin O'Toole
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a multi-level interconnect structure in a semicon...
- Patent number 11,088,070
- Issue date Aug 10, 2021
- Imec VZW
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apex angle reduction in a LED device with a LED array
- Patent number 11,005,016
- Issue date May 11, 2021
- Imec VZW
- Soeren Steudel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of patterning target layer
- Patent number 10,395,978
- Issue date Aug 27, 2019
- Imec VZW
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing germamde interconnect structures and corre...
- Patent number 9,997,458
- Issue date Jun 12, 2018
- Imec VZW
- Laure Elisa Carbonell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned interconnects
- Patent number 9,859,161
- Issue date Jan 2, 2018
- Imec VZW
- Juergen Boemmels
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Filed programmable gate array device with programmable interconnect...
- Patent number 9,553,586
- Issue date Jan 24, 2017
- Imec VZW
- Jan Genoe
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN...
- Publication number 20240234207
- Publication date Jul 11, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming an Interconnection Structure
- Publication number 20240170328
- Publication date May 23, 2024
- IMEC vzw
- Anshul Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN...
- Publication number 20240136225
- Publication date Apr 25, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUPERCONDUCTIVE INTERCONNECT STRUCTURE
- Publication number 20240038589
- Publication date Feb 1, 2024
- IMEC vzw
- Anna Yurievna HERR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metallization Process for an Integrated Circuit
- Publication number 20230197514
- Publication date Jun 22, 2023
- IMEC vzw
- Victor Hugo Vega Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING VIAS IN A SEMICONDUCTOR DEVICE
- Publication number 20210313217
- Publication date Oct 7, 2021
- TOKYO ELECTRON LIMITED
- Kaushik Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Fabrication Method for Producing Nano-Scaled Electric...
- Publication number 20210193512
- Publication date Jun 24, 2021
- IMEC vzw
- Martin O'Toole
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Via Hole Self-aligned with a Metal Block on a...
- Publication number 20210183698
- Publication date Jun 17, 2021
- IMEC vzw
- Martin O'Toole
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE IN A SEMICON...
- Publication number 20210028106
- Publication date Jan 28, 2021
- IMEC vzw
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnection System of Integrated Circuits
- Publication number 20200203273
- Publication date Jun 25, 2020
- IMEC vzw
- Stefan Cosemans
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apex Angle Reduction in a LED Device With a LED Array
- Publication number 20200185579
- Publication date Jun 11, 2020
- IMEC vzw
- Soeren Steudel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PATTERNING TARGET LAYER
- Publication number 20180247863
- Publication date Aug 30, 2018
- IMEC vzw
- Basoene Briggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED INTERCONNECTS
- Publication number 20170256451
- Publication date Sep 7, 2017
- IMEC vzw
- Juergen Boemmels
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FILED PROGRAMMABLE GATE ARRAY DEVICE WITH PROGRAMMABLE INTERCONNECT...
- Publication number 20150162913
- Publication date Jun 11, 2015
- Jan Genoe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for Manufacturing Germanide Interconnect Structures and Corr...
- Publication number 20150130062
- Publication date May 14, 2015
- IMEC vzw
- Laure Elisa Carbonell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PRODUCING A COPPER CONTACT
- Publication number 20100207177
- Publication date Aug 19, 2010
- IMEC
- Chung-Shi Liu
- H01 - BASIC ELECTRIC ELEMENTS

Zsolt Tokei

Person

Patents Grantslast 30 patents

Integrated circuit with an interconnection system having a multilev...

Method for forming a via hole self-aligned with a metal block on a...

Semiconductor fabrication method for producing nano-scaled electric...

Method of forming a multi-level interconnect structure in a semicon...

Apex angle reduction in a LED device with a LED array

Method of patterning target layer

Method for manufacturing germamde interconnect structures and corre...

Self-aligned interconnects

Filed programmable gate array device with programmable interconnect...

Patents Applicationslast 30 patents

METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN...

Method for Forming an Interconnection Structure

METHOD FOR INTERCONNECTING A BURIED WIRING LINE AND A SOURCE/DRAIN...

SUPERCONDUCTIVE INTERCONNECT STRUCTURE

Metallization Process for an Integrated Circuit

FORMING VIAS IN A SEMICONDUCTOR DEVICE

Semiconductor Fabrication Method for Producing Nano-Scaled Electric...

Method for Forming a Via Hole Self-aligned with a Metal Block on a...

METHOD OF FORMING A MULTI-LEVEL INTERCONNECT STRUCTURE IN A SEMICON...

Interconnection System of Integrated Circuits

Apex Angle Reduction in a LED Device With a LED Array

METHOD OF PATTERNING TARGET LAYER

SELF-ALIGNED INTERCONNECTS

FILED PROGRAMMABLE GATE ARRAY DEVICE WITH PROGRAMMABLE INTERCONNECT...

Method for Manufacturing Germanide Interconnect Structures and Corr...

METHOD FOR PRODUCING A COPPER CONTACT