Address circuits

Industry

CPC
G11C11/418

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements Storage elements therefor

Current Industry

G11C11/418Address circuits

Industries

Patents Grantslast 30 patents

Information Patent Grant
Current leakage management controller for reading from memory cells
- Patent number 12,148,464
- Issue date Nov 19, 2024
- Xilinx, Inc.
- Michael Tsivyan
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed synchronous write-through operation for testing two-port m...
- Patent number 12,148,490
- Issue date Nov 19, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Device signature based on trim and redundancy information
- Patent number 12,149,643
- Issue date Nov 19, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Katherine H. Chiang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with selective precharging
- Patent number 12,142,346
- Issue date Nov 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ed McCombs
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having a comparator circuit
- Patent number 12,136,454
- Issue date Nov 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jaspal Singh Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic device for configuring neural network
- Patent number 12,125,524
- Issue date Oct 22, 2024
- Samsung Electronics Co., Ltd.
- Jinseok Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and method of operating the same
- Patent number 12,125,525
- Issue date Oct 22, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Tsung-Hsien Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable delay word line enable
- Patent number 12,119,050
- Issue date Oct 15, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hyunsung Hong
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage memory device
- Patent number 12,119,052
- Issue date Oct 15, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahmut Sinangil
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and word line driver
- Patent number 12,112,796
- Issue date Oct 8, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Zhi-Hao Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device including predecoder and operating method thereof
- Patent number 12,112,795
- Issue date Oct 8, 2024
- Samsung Electronics Co., Ltd.
- Kyu Won Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive word line control circuit
- Patent number 12,106,800
- Issue date Oct 1, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chien-Chen Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Reconfigurable data processing and storage unit for deep neural net...
- Patent number 12,094,527
- Issue date Sep 17, 2024
- International Business Machines Corporation
- Rajiv Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with double redundancy
- Patent number 12,094,528
- Issue date Sep 17, 2024
- QUALCOMM Incorporated
- Dhvani Sheth
- G11 - INFORMATION STORAGE
Information Patent Grant
Serial word line actuation with linked source voltage supply modula...
- Patent number 12,087,356
- Issue date Sep 10, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell array and method of operating same
- Patent number 12,080,704
- Issue date Sep 3, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shih-Lien Linus Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device and test method for the same
- Patent number 12,073,900
- Issue date Aug 27, 2024
- Renesas Electronics Corporation
- Haruyuki Okuda
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory clock level-shifting buffer with extended range
- Patent number 12,073,876
- Issue date Aug 27, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual read port latch array bitcell
- Patent number 12,073,919
- Issue date Aug 27, 2024
- Advanced Micro Devices, Inc.
- Arijit Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-up header circuitry for multi-bank memory
- Patent number 12,068,025
- Issue date Aug 20, 2024
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
Flip flop standard cell
- Patent number 12,063,041
- Issue date Aug 13, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Nick Samra
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system with burst mode having logic gates as sense elements
- Patent number 12,057,159
- Issue date Aug 6, 2024
- Microsoft Technology Licensing, LLC
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for selective static random-access memory partiti...
- Patent number 12,046,275
- Issue date Jul 23, 2024
- Texas Instruments Incorporated
- Ruchi Shankar
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory supporting a single clock cycle read-mo...
- Patent number 12,040,013
- Issue date Jul 16, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Praveen Kumar Verma
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM circuits with aligned gate electrodes
- Patent number 12,041,761
- Issue date Jul 16, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Fang Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Split read port latch array bit cell
- Patent number 12,033,721
- Issue date Jul 9, 2024
- Advanced Micro Devices, Inc.
- Arijit Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Far end driver for memory clock
- Patent number 12,009,055
- Issue date Jun 11, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Atul Katoch
- G11 - INFORMATION STORAGE
Information Patent Grant
Weak precharge before write dual-rail SRAM write optimization
- Patent number 12,009,025
- Issue date Jun 11, 2024
- Advanced Micro Devices, Inc.
- Tawfik Ahmed
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device
- Patent number 11,990,180
- Issue date May 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shih-Lien Linus Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
FinFET semiconductor device grouping
- Patent number 11,989,498
- Issue date May 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Tzu Chen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EMBEDDED MEMORY DEVICE AND OPERATING METHOD THEREOF
- Publication number 20240386946
- Publication date Nov 21, 2024
- Samsung Electronics Co., Ltd.
- Hyunjun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE HAVING A COMPARATOR CIRCUIT
- Publication number 20240386948
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jaspal Singh SHAH
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE WORD LINE CONTROL CIRCUIT
- Publication number 20240386947
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chien-Chen Lin
- G11 - INFORMATION STORAGE
Information Patent Application
TRACKING WORST CASE MEMORY CELLS BY SUPPRESSING TRACKING WORDLINE V...
- Publication number 20240379154
- Publication date Nov 14, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yumito Aoyagi
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT AND WORD LINE DRIVER
- Publication number 20240371435
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- ZHI-HAO CHANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL ARRAY AND METHOD OF OPERATING SAME
- Publication number 20240371853
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shih-Lien Linus LU
- G11 - INFORMATION STORAGE
Information Patent Application
LOW CONTENTION CURRENT CIRCUITS
- Publication number 20240356552
- Publication date Oct 24, 2024
- Intel Corporation
- Steven Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT CELL BASED WRITE SELF-TIME DELAY PATH
- Publication number 20240331767
- Publication date Oct 3, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
BITCELL PROCESS COMPENSATED READ ASSIST SCHEME FOR SRAM
- Publication number 20240331768
- Publication date Oct 3, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNIN...
- Publication number 20240312493
- Publication date Sep 19, 2024
- Samsung Electronics Co., Ltd.
- Youngrok PARK
- G11 - INFORMATION STORAGE
Information Patent Application
OPERATION SCHEME FOR FOUR TRANSISTOR STATIC RANDOM ACCESS MEMORY
- Publication number 20240296883
- Publication date Sep 5, 2024
- FLASHSILICON INCORPORATION
- Lee Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Clock Circuitry for Memory Applications
- Publication number 20240290363
- Publication date Aug 29, 2024
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Far End Driver for Memory Clock
- Publication number 20240290366
- Publication date Aug 29, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Atul Katoch
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE USING A PLURALITY OF SUPPLY VOLTAGES AND OPERATING ME...
- Publication number 20240282367
- Publication date Aug 22, 2024
- Samsung Electronics Co., Ltd.
- Taemin Choi
- G11 - INFORMATION STORAGE
Information Patent Application
AUGMENTED MEMORY COMPUTING: A NEW PATHWAY FOR EFFICIENT AI COMPUTAT...
- Publication number 20240282366
- Publication date Aug 22, 2024
- University of Southern California
- Ajey Poovannummoottil JACOB
- G11 - INFORMATION STORAGE
Information Patent Application
Reconfigurable Compute Memory Having Selection Logic to Control Com...
- Publication number 20240249769
- Publication date Jul 25, 2024
- Numem Inc.
- Bindiganavale S. Nataraj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE AND METHOD
- Publication number 20240251540
- Publication date Jul 25, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kao-Cheng LIN
- G11 - INFORMATION STORAGE
Information Patent Application
BURST ACCESS MEMORY AND METHOD OF OPERATING A BURST ACCESS MEMORY
- Publication number 20240242761
- Publication date Jul 18, 2024
- XENERGIC AB
- Babak Mohammadi
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Port Bitcell Architecture
- Publication number 20240233814
- Publication date Jul 11, 2024
- ARM Limited
- Vianney Antoine Choserot
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION
- Publication number 20240221828
- Publication date Jul 4, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED POWER FOOTER CIRCUIT
- Publication number 20240212747
- Publication date Jun 27, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD WITH IN-MEMORY COMPUTING
- Publication number 20240211210
- Publication date Jun 27, 2024
- Samsung Electronics Co., Ltd.
- Jaerok KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM MEMORY WITH RANDOM DETERMINISTIC INITIALIZATION
- Publication number 20240203487
- Publication date Jun 20, 2024
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Jean-Philippe NOEL
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT
- Publication number 20240203488
- Publication date Jun 20, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hidehiro FUJIWARA
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT DEVICE INCLUDING AN SRAM PORTION HAVING END POWE...
- Publication number 20240203489
- Publication date Jun 20, 2024
- Mavagail Technology, LLC
- Darryl G. Walker
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR PROTECTING A PUF GENERATOR
- Publication number 20240202374
- Publication date Jun 20, 2024
- Taiwan Semiconductor Manufacturing Co., LTD
- Shih-Lien Linus LU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR OPERATING A MEMORY DEVICE
- Publication number 20240161820
- Publication date May 16, 2024
- ROBERT BOSCH GmbH
- Taha Soliman
- G11 - INFORMATION STORAGE
Information Patent Application
Buried Metal Techniques for Memory Applications
- Publication number 20240153551
- Publication date May 9, 2024
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Port Bitcell Architecture
- Publication number 20240135988
- Publication date Apr 25, 2024
- ARM Limited
- Vianney Antoine Choserot
- G11 - INFORMATION STORAGE
Information Patent Application
ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...
- Publication number 20240112728
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE

Address circuits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Current leakage management controller for reading from memory cells

At-speed synchronous write-through operation for testing two-port m...

Device signature based on trim and redundancy information

Memory device with selective precharging

Memory device having a comparator circuit

Electronic device for configuring neural network

Memory device and method of operating the same

Variable delay word line enable

Low voltage memory device

Memory circuit and word line driver

Memory device including predecoder and operating method thereof

Adaptive word line control circuit

Reconfigurable data processing and storage unit for deep neural net...

Memory with double redundancy

Serial word line actuation with linked source voltage supply modula...

Memory cell array and method of operating same

Semiconductor memory device and test method for the same

Memory clock level-shifting buffer with extended range

Dual read port latch array bitcell

Power-up header circuitry for multi-bank memory

Flip flop standard cell

Memory system with burst mode having logic gates as sense elements

System and method for selective static random-access memory partiti...

Static random access memory supporting a single clock cycle read-mo...

SRAM circuits with aligned gate electrodes

Split read port latch array bit cell

Far end driver for memory clock

Weak precharge before write dual-rail SRAM write optimization

Memory device

FinFET semiconductor device grouping

Patents Applicationslast 30 patents

EMBEDDED MEMORY DEVICE AND OPERATING METHOD THEREOF

MEMORY DEVICE HAVING A COMPARATOR CIRCUIT

ADAPTIVE WORD LINE CONTROL CIRCUIT

TRACKING WORST CASE MEMORY CELLS BY SUPPRESSING TRACKING WORDLINE V...

MEMORY CIRCUIT AND WORD LINE DRIVER

MEMORY CELL ARRAY AND METHOD OF OPERATING SAME

LOW CONTENTION CURRENT CIRCUITS

BIT CELL BASED WRITE SELF-TIME DELAY PATH

BITCELL PROCESS COMPENSATED READ ASSIST SCHEME FOR SRAM

INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNIN...

OPERATION SCHEME FOR FOUR TRANSISTOR STATIC RANDOM ACCESS MEMORY

Clock Circuitry for Memory Applications

Far End Driver for Memory Clock

MEMORY DEVICE USING A PLURALITY OF SUPPLY VOLTAGES AND OPERATING ME...

AUGMENTED MEMORY COMPUTING: A NEW PATHWAY FOR EFFICIENT AI COMPUTAT...

Reconfigurable Compute Memory Having Selection Logic to Control Com...

INTEGRATED CIRCUIT DEVICE AND METHOD

BURST ACCESS MEMORY AND METHOD OF OPERATING A BURST ACCESS MEMORY

Multi-Port Bitcell Architecture

HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION

SHARED POWER FOOTER CIRCUIT

APPARATUS AND METHOD WITH IN-MEMORY COMPUTING

SRAM MEMORY WITH RANDOM DETERMINISTIC INITIALIZATION

STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT

INTEGRATED CIRCUIT DEVICE INCLUDING AN SRAM PORTION HAVING END POWE...

METHOD AND APPARATUS FOR PROTECTING A PUF GENERATOR

METHOD AND DEVICE FOR OPERATING A MEMORY DEVICE

Buried Metal Techniques for Memory Applications

Multi-Port Bitcell Architecture

ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...