Address generation devices Devices for accessing memories

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G11C29/18

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/18Address generation devices Devices for accessing memories

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Dynamic address scramble
- Patent number 12,334,138
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Erik T. Barmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Repairable semiconductor memory device
- Patent number 12,315,583
- Issue date May 27, 2025
- ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
- Min-Chung Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable MBIST method based on adaptive march algorithm
- Patent number 12,308,085
- Issue date May 20, 2025
- Nanjing University Of Posts And Telecommunications
- Zhikuang Cai
- G11 - INFORMATION STORAGE
Information Patent Grant
Test circuit and receiving circuit having test function
- Patent number 12,288,589
- Issue date Apr 29, 2025
- SK hynix Inc.
- Gi Moon Hong
- G11 - INFORMATION STORAGE
Information Patent Grant
Test circuit for detecting word line defect and semiconductor appar...
- Patent number 12,283,331
- Issue date Apr 22, 2025
- SK hynix Inc.
- Suk Hwan Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit retiring to mitigate bit errors
- Patent number 12,283,333
- Issue date Apr 22, 2025
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory BIST circuit and method
- Patent number 12,283,332
- Issue date Apr 22, 2025
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Technologies for repair of memory with access lines
- Patent number 12,277,985
- Issue date Apr 15, 2025
- Intel Corporation
- William K. Waller
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self-test circuit for row hammering in memory
- Patent number 12,266,413
- Issue date Apr 1, 2025
- Synopsys, Inc.
- Grigor Tshagharyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method for performing test
- Patent number 12,254,937
- Issue date Mar 18, 2025
- SK hynix Inc.
- Choung Ki Song
- G11 - INFORMATION STORAGE
Information Patent Grant
System and memory with configurable metadata portion
- Patent number 12,230,347
- Issue date Feb 18, 2025
- QUALCOMM Incorporated
- Jungwon Suh
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and information processing system for testing storage...
- Patent number 12,224,027
- Issue date Feb 11, 2025
- Kioxia Corporation
- Masayoshi Sato
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device and memory system performing error corr...
- Patent number 12,224,026
- Issue date Feb 11, 2025
- SK Hynix Inc.
- Hong Ki Moon
- G11 - INFORMATION STORAGE
Information Patent Grant
Burst indicator systems and methods
- Patent number 12,211,573
- Issue date Jan 28, 2025
- Micron Technology, Inc.
- Kai Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for error correction coding with multiple hash groupings and...
- Patent number 12,211,574
- Issue date Jan 28, 2025
- Taiwan Semiconductor Manufacturing Company Limited
- Katherine H. Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and memory system including the same
- Patent number 12,205,661
- Issue date Jan 21, 2025
- Samsung Electronics Co., Ltd.
- Sung-Rae Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory and operation method thereof
- Patent number 12,190,982
- Issue date Jan 7, 2025
- SK Hynix Inc.
- Seung Chan Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for protecting memory devices via a synergic a...
- Patent number 12,175,087
- Issue date Dec 24, 2024
- SeyedMohammad SeyedzadehDelcheh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data writing method, test method, writing apparatus, medium, and el...
- Patent number 12,159,680
- Issue date Dec 3, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Yuanyuan Sun
- G11 - INFORMATION STORAGE
Information Patent Grant
Test systems configured to perform test mode operations for multipl...
- Patent number 12,159,681
- Issue date Dec 3, 2024
- SK hynix Inc.
- Sang Ah Hyun
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and semiconductor system for detecting an erro...
- Patent number 12,148,492
- Issue date Nov 19, 2024
- SK hynix Inc.
- Yeong Han Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing system and testing method
- Patent number 12,142,340
- Issue date Nov 12, 2024
- Realtek Semiconductor Corporation
- Shih-Chieh Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for parallel memory test
- Patent number 12,142,337
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Nitesh Mishra
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor system including semiconductor device for performing...
- Patent number 12,131,791
- Issue date Oct 29, 2024
- SK Hynix Inc.
- Byung Goo Cho
- G11 - INFORMATION STORAGE
Information Patent Grant
RAM test with parity error detection and handling
- Patent number 12,130,700
- Issue date Oct 29, 2024
- Hamilton Sundstrand Corporation
- Qiuming Leng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system
- Patent number 12,068,049
- Issue date Aug 20, 2024
- Kioxia Corporation
- Naomi Takeda
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for generating command sequence, method and devic...
- Patent number 12,040,030
- Issue date Jul 16, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Yu Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for detecting errors in a memory device
- Patent number 12,009,041
- Issue date Jun 11, 2024
- ARM Limited
- Siddharth Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Command/address channel error detection
- Patent number 12,002,532
- Issue date Jun 4, 2024
- RAMBUS INC.
- John Eric Linstadt
- G11 - INFORMATION STORAGE
Information Patent Grant
Hardware accelerator device, corresponding system and method of ope...
- Patent number 11,996,158
- Issue date May 28, 2024
- STMicroelectronics S.r.l.
- Giampiero Borgonovo
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE INCLUDING BUILT-IN-SELF-TES...
- Publication number 20250191671
- Publication date Jun 12, 2025
- Samsung Electronics Co., Ltd.
- Jaehyeok KIM
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR SYSTEM FOR DETECTING FAIL LOCATION
- Publication number 20250140333
- Publication date May 1, 2025
- SK HYNIX INC.
- Dong Yoon KA
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC SYSTEM RELATED TO DETECTING A RESULT OF A RUPTURE OPERATION
- Publication number 20250125002
- Publication date Apr 17, 2025
- SK HYNIX INC.
- Dong Beom LEE
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR ERROR CORRECTION CODING WITH MULTIPLE HASH GROUPINGS AND...
- Publication number 20250124997
- Publication date Apr 17, 2025
- Taiwan Semiconductor Manufacturing Company Limited
- Katherine H. CHIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND MEMORY WITH CONFIGURABLE METADATA PORTION
- Publication number 20250111885
- Publication date Apr 3, 2025
- QUALCOMM Incorporated
- Jungwon Suh
- G11 - INFORMATION STORAGE
Information Patent Application
FAILURE ANALYSIS DEVICE AND FAILURE ANALYSIS METHOD
- Publication number 20250111882
- Publication date Apr 3, 2025
- RENESAS ELECTRONICS CORPORATION
- Toru OGUSHI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE, TEST METHOD OF THE MEMORY DEVICE, AND METHOD OF MANU...
- Publication number 20250104791
- Publication date Mar 27, 2025
- Samsung Electronics Co., Ltd.
- Jaewon Park
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS INCLUDING BTI CONTROLLER
- Publication number 20250104792
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- YASUSHI MATSUBARA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY AND OPERATION METHOD THEREOF
- Publication number 20250095769
- Publication date Mar 20, 2025
- SK HYNIX INC.
- Seung Chan KIM
- G11 - INFORMATION STORAGE
Information Patent Application
Row Repair Circuitry
- Publication number 20250087296
- Publication date Mar 13, 2025
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
- Publication number 20250078947
- Publication date Mar 6, 2025
- Samsung Electronics Co., Ltd.
- Sung-Rae KIM
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH MULTIPLE DATA RESOLUTIONS
- Publication number 20250037783
- Publication date Jan 30, 2025
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
RECONFIGURABLE MBIST METHOD BASED ON ADAPTIVE MARCH ALGORITHM
- Publication number 20250006289
- Publication date Jan 2, 2025
- Nanjing University Of Posts And Telecommunications
- Zhikuang CAI
- G11 - INFORMATION STORAGE
Information Patent Application
Fully Scannable Memory Arrays
- Publication number 20240412797
- Publication date Dec 12, 2024
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Scanning a Memory Array
- Publication number 20240412798
- Publication date Dec 12, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
BYPASS BUFFER FOR WORN OUT CODEWORDS
- Publication number 20240386981
- Publication date Nov 21, 2024
- Western Digital Technologies, Inc.
- Lunkai Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM
- Publication number 20240363186
- Publication date Oct 31, 2024
- KIOXIA Corporation
- Naomi TAKEDA
- G11 - INFORMATION STORAGE
Information Patent Application
APPRATUS AND METHOD FOR CHANGING A READ VOLTAGE APPLIED FOR READING...
- Publication number 20240355405
- Publication date Oct 24, 2024
- SK HYNIX INC.
- Jae Yong SON
- G11 - INFORMATION STORAGE
Information Patent Application
COMMAND/ADDRESS CHANNEL ERROR DETECTION
- Publication number 20240355407
- Publication date Oct 24, 2024
- Rambus Inc.
- John Eric Linstadt
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE USING HOST MEMORY BUFFER AND METHOD OF OPERATING THE...
- Publication number 20240338124
- Publication date Oct 10, 2024
- Samsung Electronics Co., Ltd.
- Jongmin KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE DEVICE FOR SUPPORTING DYNAMIC ALLOCATION OF MEMORY AND METH...
- Publication number 20240331790
- Publication date Oct 3, 2024
- SK HYNIX INC.
- Tae Ho LIM
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR TESTING MEMORY DEVICES
- Publication number 20240331794
- Publication date Oct 3, 2024
- Micron Technology, Inc.
- TAKAMASA SUZUKI
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR STORING ERROR INFORMATION AND...
- Publication number 20240312547
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Sujeet Ayyapureddi
- G11 - INFORMATION STORAGE
Information Patent Application
RAM TEST WITH PARITY ERROR DETECTION AND HANDLING
- Publication number 20240296087
- Publication date Sep 5, 2024
- HAMILTON SUNDSTRAND CORPORATION
- Qiuming Leng
- G11 - INFORMATION STORAGE
Information Patent Application
BIT RETIRING TO MITIGATE BIT ERRORS
- Publication number 20240265991
- Publication date Aug 8, 2024
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
COMMAND ADDRESS CONTROL CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SE...
- Publication number 20240257891
- Publication date Aug 1, 2024
- SK HYNIX INC.
- Ji Hwan PARK
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM
- Publication number 20240257894
- Publication date Aug 1, 2024
- SK HYNIX INC.
- Chul Moon JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE INCLUDING REPAIR CIRCUIT AND OPERATING METHOD THEREOF
- Publication number 20240257896
- Publication date Aug 1, 2024
- Samsung Electronics Co., Ltd.
- Seungki HONG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM
- Publication number 20240257895
- Publication date Aug 1, 2024
- SK HYNIX INC.
- Chul Moon JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
TEST CIRCUIT AND RECEIVING CIRCUIT HAVING TEST FUNCTION
- Publication number 20240242773
- Publication date Jul 18, 2024
- SK HYNIX INC.
- Gi Moon HONG
- G11 - INFORMATION STORAGE

Address generation devices Devices for accessing memories

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Dynamic address scramble

Repairable semiconductor memory device

Reconfigurable MBIST method based on adaptive march algorithm

Test circuit and receiving circuit having test function

Test circuit for detecting word line defect and semiconductor appar...

Bit retiring to mitigate bit errors

Memory BIST circuit and method

Technologies for repair of memory with access lines

Built-in self-test circuit for row hammering in memory

Semiconductor device and method for performing test

System and memory with configurable metadata portion

Memory system and information processing system for testing storage...

Semiconductor memory device and memory system performing error corr...

Burst indicator systems and methods

Method for error correction coding with multiple hash groupings and...

Memory device and memory system including the same

Memory and operation method thereof

Method and apparatus for protecting memory devices via a synergic a...

Data writing method, test method, writing apparatus, medium, and el...

Test systems configured to perform test mode operations for multipl...

Semiconductor device and semiconductor system for detecting an erro...

Testing system and testing method

System and method for parallel memory test

Semiconductor system including semiconductor device for performing...

RAM test with parity error detection and handling

Memory system

Method and device for generating command sequence, method and devic...

Apparatus and method for detecting errors in a memory device

Command/address channel error detection

Hardware accelerator device, corresponding system and method of ope...

Patents Applicationslast 30 patents

BUILT-IN-SELF-TEST LOGIC, MEMORY DEVICE INCLUDING BUILT-IN-SELF-TES...

SEMICONDUCTOR SYSTEM FOR DETECTING FAIL LOCATION

ELECTRONIC SYSTEM RELATED TO DETECTING A RESULT OF A RUPTURE OPERATION

METHOD FOR ERROR CORRECTION CODING WITH MULTIPLE HASH GROUPINGS AND...

SYSTEM AND MEMORY WITH CONFIGURABLE METADATA PORTION

FAILURE ANALYSIS DEVICE AND FAILURE ANALYSIS METHOD

MEMORY DEVICE, TEST METHOD OF THE MEMORY DEVICE, AND METHOD OF MANU...

APPARATUS INCLUDING BTI CONTROLLER

MEMORY AND OPERATION METHOD THEREOF

Row Repair Circuitry

MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

NON-VOLATILE MEMORY WITH MULTIPLE DATA RESOLUTIONS

RECONFIGURABLE MBIST METHOD BASED ON ADAPTIVE MARCH ALGORITHM

Fully Scannable Memory Arrays

Method for Scanning a Memory Array

BYPASS BUFFER FOR WORN OUT CODEWORDS

MEMORY SYSTEM

APPRATUS AND METHOD FOR CHANGING A READ VOLTAGE APPLIED FOR READING...

COMMAND/ADDRESS CHANNEL ERROR DETECTION

STORAGE DEVICE USING HOST MEMORY BUFFER AND METHOD OF OPERATING THE...

STORAGE DEVICE FOR SUPPORTING DYNAMIC ALLOCATION OF MEMORY AND METH...

APPARATUSES AND METHODS FOR TESTING MEMORY DEVICES

APPARATUSES, SYSTEMS, AND METHODS FOR STORING ERROR INFORMATION AND...

RAM TEST WITH PARITY ERROR DETECTION AND HANDLING

BIT RETIRING TO MITIGATE BIT ERRORS

COMMAND ADDRESS CONTROL CIRCUIT, AND SEMICONDUCTOR APPARATUS AND SE...

MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM

MEMORY DEVICE INCLUDING REPAIR CIRCUIT AND OPERATING METHOD THEREOF

MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM

TEST CIRCUIT AND RECEIVING CIRCUIT HAVING TEST FUNCTION