Assembly of a plurality of insulating substrates

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H01L23/5385

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L23/00Details of semiconductor or other solid state devices

Current Industry

H01L23/5385Assembly of a plurality of insulating substrates

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Patents Grantslast 30 patents

Information Patent Grant
Electronic package
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- Issue date Jul 22, 2025
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Method for producing semiconductor apparatus and semiconductor appa...
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Information Patent Grant
Hybrid integrated circuit packages
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High bandwidth die to die interconnect with package area reduction
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Information Patent Grant
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Information Patent Grant
Three-dimensional integrated circuit
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Information Patent Grant
Semiconductor device with redistribution structure and method for f...
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Package comprising a substrate and a high-density interconnect inte...
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Lithographic cavity formation to enable EMIB bump pitch scaling
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Information Patent Grant
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Logic die in a multi-chip package having a configurable physical in...
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Integrated circuit package with decoupling capacitors
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Interconnection structure and semiconductor package including the same
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Information Patent Grant
Interconnect architecture with silicon interposer and EMIB
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- Md Altaf Hossain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies with direct attach to circuit boards
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Microelectronic assemblies having a hybrid bonded interposer for di...
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Substrateless double-sided embedded multi-die interconnect bridge
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Electronic package and manufacturing method thereof
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Information Patent Grant
Encapsulated package including device dies connected via interconne...
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Information Patent Grant
Lithographic cavity formation to enable EMIB bump pitch scaling
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- Kristof Darmawikarta
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Information Patent Grant
Die coupling using a substrate with a glass core
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Information Patent Grant
Semiconductor package including redistribution substrate
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- Issue date Jun 10, 2025
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- Dongkyu Kim
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Information Patent Grant
Eccentric via structures for stress reduction
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- Issue date Jun 3, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Shu-Shen Yeh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

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SEMICONDUCTOR PACKAGE
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COMMUNICATION SYSTEM BETWEEN DIES AND OPERATION METHOD THEREOF
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- G06 - COMPUTING CALCULATING COUNTING
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SEMICONDUCTOR PACKAGE ASSEMBLY WITH AN INTERLAYER COOLING PATHWAY
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ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF
- Publication number 20250226326
- Publication date Jul 10, 2025
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COMMUNICATION SYSTEM BETWEEN DIES AND OPERATION METHOD THEREOF
- Publication number 20250225101
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PHOTOELECTRIC DEVICE, OPTICAL TRANSCEIVER, AND METHOD OF OPERATING...
- Publication number 20250226373
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- YOU-CHENG LU
- H01 - BASIC ELECTRIC ELEMENTS
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ELECTROLESS NICKEL-ELECTROLESS PALLADIUM-IMMERSION GOLD (ENEPIG) AS...
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- Prithwish Chatterjee
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SEMICONDUCTOR PACKAGE
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HYBRID BONDING STRUCTURE AND DISPLAY PANEL
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ELECTROLESS NICKEL-ELECTROLESS PALLADIUM-IMMERSION GOLD (ENEPIG) WI...
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PACKAGE AND METHOD FOR MANUFACTURING PACKAGE
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SEMICONDUCTOR PACKAGE
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- JIWON SHIN
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STACKED PACKAGE DEVICE WITH INTERCONNECTED SUBSTRATES
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- HUNG HSIN HSU
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SEMICONDUCTOR PACKAGE
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- Sang Ho SHIN
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INTEGRATED CIRCUIT PACKAGES WITH THERMAL RESERVOIR DIES AND METHODS...
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- Lipu Kris Chuang
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DISPLAY DEVICE
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- Kyungkyu KIM
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SEMICONDUCTOR DEVICE
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- ROHM CO., LTD.
- Oji SATO
- H01 - BASIC ELECTRIC ELEMENTS
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PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
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- Samsung Electronics Co., Ltd.
- Minjin Kim
- H01 - BASIC ELECTRIC ELEMENTS
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INTEGRATED CIRCUIT PACKAGES WITH STIFFENERS CONTAINING SEMICONDUCTO...
- Publication number 20250210429
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- Jackson Chung Peng Kong
- H01 - BASIC ELECTRIC ELEMENTS
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STACKED PACKAGE DEVICE WITH INTERCONNECTED CONDUCTIVE BUMPS
- Publication number 20250210482
- Publication date Jun 26, 2025
- Powertech Technology Inc.
- HUNG HSIN HSU
- H01 - BASIC ELECTRIC ELEMENTS

Assembly of a plurality of insulating substrates

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Electronic package

Method for producing semiconductor apparatus and semiconductor appa...

Hybrid integrated circuit packages

High bandwidth die to die interconnect with package area reduction

Parameter exchange for a die-to-die interconnect

Semiconductor structure and manufacturing method thereof

Composite interposer structure and method of providing same

Three-dimensional integrated circuit

Semiconductor device with redistribution structure and method for f...

Package comprising a substrate and a high-density interconnect inte...

Lithographic cavity formation to enable EMIB bump pitch scaling

Logic drive based on chip scale package comprising standardized com...

Reconstituted substrate structure and fabrication methods for heter...

Logic die in a multi-chip package having a configurable physical in...

Semiconductor devices having penetration vias

Integrated circuit package with decoupling capacitors

Interconnection structure and semiconductor package including the same

Interconnect architecture with silicon interposer and EMIB

Microelectronic assemblies with direct attach to circuit boards

Microelectronic assemblies having a hybrid bonded interposer for di...

Bare-die smart bridge connected with copper pillars for system-in-p...

Semiconductor device

Substrateless double-sided embedded multi-die interconnect bridge

Electronic package and manufacturing method thereof

Encapsulated package including device dies connected via interconne...

Lithographic cavity formation to enable EMIB bump pitch scaling

Die coupling using a substrate with a glass core

ASIC package with photonics and vertical power delivery

Semiconductor package including redistribution substrate

Eccentric via structures for stress reduction

Patents Applicationslast 30 patents

ELECTRONIC PACKAGE AND MANUFACTURING METHOD OF ELECTRONIC PACKAGE

SEMICONDUCTOR MODULE

ELECTRONIC DEVICE

ELECTRONIC DEVICE AND A METHOD FOR FORMING THE SAME

SEMICONDUCTOR PACKAGE

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE...

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE...

COMMUNICATION SYSTEM BETWEEN DIES AND OPERATION METHOD THEREOF

SEMICONDUCTOR PACKAGE ASSEMBLY WITH AN INTERLAYER COOLING PATHWAY

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

COMMUNICATION SYSTEM BETWEEN DIES AND OPERATION METHOD THEREOF

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

PHOTOELECTRIC DEVICE, OPTICAL TRANSCEIVER, AND METHOD OF OPERATING...

ELECTROLESS NICKEL-ELECTROLESS PALLADIUM-IMMERSION GOLD (ENEPIG) AS...

SEMICONDUCTOR PACKAGE

HYBRID BONDING STRUCTURE AND DISPLAY PANEL

POWER MODULES

ELECTROLESS NICKEL-ELECTROLESS PALLADIUM-IMMERSION GOLD (ENEPIG) WI...

SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME

PACKAGE AND METHOD FOR MANUFACTURING PACKAGE

SEMICONDUCTOR PACKAGE

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

STACKED PACKAGE DEVICE WITH INTERCONNECTED SUBSTRATES

SEMICONDUCTOR PACKAGE

INTEGRATED CIRCUIT PACKAGES WITH THERMAL RESERVOIR DIES AND METHODS...

DISPLAY DEVICE

SEMICONDUCTOR DEVICE

PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

INTEGRATED CIRCUIT PACKAGES WITH STIFFENERS CONTAINING SEMICONDUCTO...

STACKED PACKAGE DEVICE WITH INTERCONNECTED CONDUCTIVE BUMPS