being inert

Industry

CPC
H01L2224/80075

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/80075being inert

Industries

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor structure
- Patent number 12,009,323
- Issue date Jun 11, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chia-Yu Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive barrier direct hybrid bonding
- Patent number 11,830,838
- Issue date Nov 28, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Front-to-back bonding with through-substrate via (TSV)
- Patent number 11,791,241
- Issue date Oct 17, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid bonding with through substrate via (TSV)
- Patent number 11,658,172
- Issue date May 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and method for forming the same
- Patent number 11,456,263
- Issue date Sep 27, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chia-Yu Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive barrier direct hybrid bonding
- Patent number 11,264,345
- Issue date Mar 1, 2022
- INVENSAS BONDING TECHNOLOGIES, INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Front-to-back bonding with through-substrate via (TSV)
- Patent number 10,847,443
- Issue date Nov 24, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device for bonding conductive layers exposed from sur...
- Patent number 10,840,204
- Issue date Nov 17, 2020
- TOSHIBA MEMORY CORPORATION
- Atsuko Kawasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gas-controlled bonding platform for edge defect reduction during wa...
- Patent number 10,777,433
- Issue date Sep 15, 2020
- ELPIS TECHNOLOGIES INC.
- Wei Lin
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor structure and method for forming the same
- Patent number 10,692,826
- Issue date Jun 23, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chia-Yu Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid bonding systems and methods for semiconductor wafers
- Patent number 10,354,972
- Issue date Jul 16, 2019
- Taiwan Semiconductor Manufacturing Company
- Ping-Yin Liu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Direct bonding method
- Patent number 10,236,210
- Issue date Mar 19, 2019
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Aurélie Tauzin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid bonding systems and methods for semiconductor wafers
- Patent number 10,103,122
- Issue date Oct 16, 2018
- Taiwan Semiconductor Manufacturing Company
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mechanisms for forming three-dimensional integrated circuit (3DIC)...
- Patent number 9,929,050
- Issue date Mar 27, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for verification of bonding alignment
- Patent number 9,842,785
- Issue date Dec 12, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Xin-Hua Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Front-to-back bonding with through-substrate via (TSV)
- Patent number 9,831,156
- Issue date Nov 28, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid bonding systems and methods for semiconductor wafers
- Patent number 9,748,198
- Issue date Aug 29, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for verification of bonding alignment
- Patent number 9,478,471
- Issue date Oct 25, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Xin-Hua Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor apparatus, electronic device, and method of manufactu...
- Patent number 9,379,006
- Issue date Jun 28, 2016
- Sony Corporation
- Yoshihisa Kagawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flattened substrate surface for substrate bonding
- Patent number 9,355,936
- Issue date May 31, 2016
- GLOBALFOUNDRIES Inc.
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid bonding and apparatus for performing the same
- Patent number 9,331,032
- Issue date May 3, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Front-to-back bonding with through-substrate via (TSV)
- Patent number 9,299,640
- Issue date Mar 29, 2016
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid bonding systems and methods for semiconductor wafers
- Patent number 9,048,283
- Issue date Jun 2, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for bonding of chips on wafers
- Patent number 8,927,335
- Issue date Jan 6, 2015
- EV Group E. Thallner GmbH
- Markus Wimplinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor apparatus, electronic device, and method of manufactu...
- Patent number 8,664,763
- Issue date Mar 4, 2014
- Sony Corporation
- Yoshihisa Kagawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional (3D) integrated circuit with enhanced copper-to-c...
- Patent number 8,546,956
- Issue date Oct 1, 2013
- International Business Machines Corporation
- Son V. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional (3D) integrated circuit with enhanced copper-to-c...
- Patent number 8,431,436
- Issue date Apr 30, 2013
- International Business Machines Corporation
- Son V. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CONDUCTIVE BARRIER DIRECT HYBRID BONDING
- Publication number 20240243085
- Publication date Jul 18, 2024
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Paul M. Enquist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER BONDING METHOD USING SELECTIVE DEPOSITION AND SURFACE TREATMENT
- Publication number 20230075263
- Publication date Mar 9, 2023
- TOKYO ELECTRON LIMITED
- Soo Doo Chae
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE
- Publication number 20220367391
- Publication date Nov 17, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chia-Yu WEI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE BARRIER DIRECT HYBRID BONDING
- Publication number 20220254746
- Publication date Aug 11, 2022
- INVENSAS BONDING TECHNOLOGIES, INC.
- Paul M. ENQUIST
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FRONT-TO-BACK BONDING WITH THROUGH-SUBSTRATE VIA (TSV)
- Publication number 20210043547
- Publication date Feb 11, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jing-Cheng LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20200321294
- Publication date Oct 8, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chia-Yu WEI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE FOR BONDING CONDUCTIVE LAYERS EXPOSED FROM SUR...
- Publication number 20200126941
- Publication date Apr 23, 2020
- Toshiba Memory Corporation
- Atsuko KAWASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)
- Publication number 20200027868
- Publication date Jan 23, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jing-Cheng LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE BARRIER DIRECT HYBRID BONDING
- Publication number 20190237419
- Publication date Aug 1, 2019
- INVENSAS BONDING TECHNOLOGIES, INC.
- Paul M. ENQUIST
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20190096830
- Publication date Mar 28, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chia-Yu WEI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hybrid Bonding Systems and Methods for Semiconductor Wafers
- Publication number 20190051628
- Publication date Feb 14, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FRONT-TO-BACK BONDING WITH THROUGH-SUBSTRATE VIA (TSV)
- Publication number 20180145011
- Publication date May 24, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jing-Cheng LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hybrid Bonding Systems and Methods for Semiconductor Wafers
- Publication number 20170358551
- Publication date Dec 14, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hybrid Bonding and Apparatus for Performing the Same
- Publication number 20140256087
- Publication date Sep 11, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING
- Publication number 20140209908
- Publication date Jul 31, 2014
- International Business Machines Corporation
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR APPARATUS, ELECTRONIC DEVICE, AND METHOD OF MANUFACTU...
- Publication number 20140131874
- Publication date May 15, 2014
- SONY CORPORATION
- Yoshihisa Kagawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hybrid Bonding Systems and Methods for Semiconductor Wafers
- Publication number 20140011324
- Publication date Jan 9, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ping-Yin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-C...
- Publication number 20130200520
- Publication date Aug 8, 2013
- International Business Machines Corporation
- Son V. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-C...
- Publication number 20130113106
- Publication date May 9, 2013
- International Business Machines Corporation
- Son V. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING
- Publication number 20130105981
- Publication date May 2, 2013
- International Business Machines Corporation
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR APPARATUS, ELECTRONIC DEVICE, AND METHOD OF MANUFACTU...
- Publication number 20120241961
- Publication date Sep 27, 2012
- SONY CORPORATION
- Yoshihisa Kagawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR BONDING OF CHIPS ON WAFERS
- Publication number 20120184069
- Publication date Jul 19, 2012
- Markus Wimplinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Alignment and Bonding System
- Publication number 20100122456
- Publication date May 20, 2010
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS

being inert

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor structure

Conductive barrier direct hybrid bonding

Front-to-back bonding with through-substrate via (TSV)

Hybrid bonding with through substrate via (TSV)

Semiconductor structure and method for forming the same

Conductive barrier direct hybrid bonding

Front-to-back bonding with through-substrate via (TSV)

Semiconductor device for bonding conductive layers exposed from sur...

Gas-controlled bonding platform for edge defect reduction during wa...

Semiconductor structure and method for forming the same

Hybrid bonding systems and methods for semiconductor wafers

Direct bonding method

Hybrid bonding systems and methods for semiconductor wafers

Mechanisms for forming three-dimensional integrated circuit (3DIC)...

Apparatus and method for verification of bonding alignment

Front-to-back bonding with through-substrate via (TSV)

Hybrid bonding systems and methods for semiconductor wafers

Apparatus and method for verification of bonding alignment

Semiconductor apparatus, electronic device, and method of manufactu...

Flattened substrate surface for substrate bonding

Hybrid bonding and apparatus for performing the same

Front-to-back bonding with through-substrate via (TSV)

Hybrid bonding systems and methods for semiconductor wafers

Method for bonding of chips on wafers

Semiconductor apparatus, electronic device, and method of manufactu...

Three-dimensional (3D) integrated circuit with enhanced copper-to-c...

Three-dimensional (3D) integrated circuit with enhanced copper-to-c...

Patents Applicationslast 30 patents

CONDUCTIVE BARRIER DIRECT HYBRID BONDING

WAFER BONDING METHOD USING SELECTIVE DEPOSITION AND SURFACE TREATMENT

SEMICONDUCTOR STRUCTURE

CONDUCTIVE BARRIER DIRECT HYBRID BONDING

FRONT-TO-BACK BONDING WITH THROUGH-SUBSTRATE VIA (TSV)

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR DEVICE FOR BONDING CONDUCTIVE LAYERS EXPOSED FROM SUR...

HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

CONDUCTIVE BARRIER DIRECT HYBRID BONDING

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Hybrid Bonding Systems and Methods for Semiconductor Wafers

FRONT-TO-BACK BONDING WITH THROUGH-SUBSTRATE VIA (TSV)

Hybrid Bonding Systems and Methods for Semiconductor Wafers

Hybrid Bonding and Apparatus for Performing the Same

FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING

SEMICONDUCTOR APPARATUS, ELECTRONIC DEVICE, AND METHOD OF MANUFACTU...

Hybrid Bonding Systems and Methods for Semiconductor Wafers

THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-C...

THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-C...

FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING

SEMICONDUCTOR APPARATUS, ELECTRONIC DEVICE, AND METHOD OF MANUFACTU...

METHOD FOR BONDING OF CHIPS ON WAFERS

Integrated Alignment and Bonding System