Capping layer

Industry

CPC
Y10S148/015

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YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10USPC classification Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10S148/00Metal treatment

Current Industry

Y10S148/015Capping layer

Industries

Patents Grantslast 30 patents

Information Patent Grant
Refractory metal capped low resistivity metal conductor lines and v...
- Patent number 6,323,554
- Issue date Nov 27, 2001
- International Business Machines Corporation
- Rajiv V. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Refractory metal capped low resistivity metal conductor lines and vias
- Patent number 6,147,402
- Issue date Nov 14, 2000
- International Business Machines Corporation
- Rajiv V. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Refractory metal capped low resistivity metal conductor lines and vias
- Patent number 5,976,975
- Issue date Nov 2, 1999
- International Business Machines Corporation
- Rajiv V. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device and semiconductor de...
- Patent number 5,923,073
- Issue date Jul 13, 1999
- Kabushiki Kaisha Toshiba
- Masami Aoki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Refractory metal capped low resistivity metal conductor lines and vias
- Patent number 5,889,328
- Issue date Mar 30, 1999
- International Business Machines Corporation
- Rajiv V. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of manufacturing the same
- Patent number 5,763,953
- Issue date Jun 9, 1998
- Kabushiki Kaisha Toshiba
- Tadashi Iijima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Refractory metal capped low resistivity metal conductor lines and vias
- Patent number 5,585,673
- Issue date Dec 17, 1996
- International Business Machines Corporation
- Rajiv V. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming titanium silicide local interconnect
- Patent number 5,543,361
- Issue date Aug 6, 1996
- AT&T Global Information Solutions Company
- Steven S. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of diffusing a metal through a silver electrode to form a pr...
- Patent number 5,529,954
- Issue date Jun 25, 1996
- Kabushiki Kaisha Toshiba
- Tadashi Iijima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer aluminum wiring in semiconductor IC
- Patent number 5,519,254
- Issue date May 21, 1996
- Yamaha Corporation
- Suguru Tabara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming titanium silicide local interconnect
- Patent number 5,443,996
- Issue date Aug 22, 1995
- AT&T Global Information Solutions Company
- Steven S. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to prevent silicide bubble in the VLSI process
- Patent number 5,434,096
- Issue date Jul 18, 1995
- Taiwan Semiconductor Manufacturing Company LTD.
- Cheng-Te Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a complementary heterojunction FET
- Patent number 5,427,965
- Issue date Jun 27, 1995
- Motorola, Inc.
- Saied N. Tehrani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Refractory metal capped low resistivity metal conductor lines and vias
- Patent number 5,426,330
- Issue date Jun 20, 1995
- International Business Machines Corporation
- Rajiv V. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Refractory metal capped low resistivity metal conductor lines and v...
- Patent number 5,403,779
- Issue date Apr 4, 1995
- International Business Machines Corporation
- Rajiv V. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming multilayer aluminum wiring in semiconductor IC
- Patent number 5,399,527
- Issue date Mar 21, 1995
- Yamaha Corporation
- Suguru Tabara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device isolated by a trench
- Patent number 5,384,280
- Issue date Jan 24, 1995
- Kabushiki Kaisha Toshiba
- Masami Aoki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device, in which a metal co...
- Patent number 5,366,928
- Issue date Nov 22, 1994
- U.S. Philips Corporation
- Robertus A. M. Wolters
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Complementary heterojunction device
- Patent number 5,349,214
- Issue date Sep 20, 1994
- Motorola, Inc.
- Saied N. Tehrani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming isolated regions of oxide
- Patent number 5,338,968
- Issue date Aug 16, 1994
- SGS-Thomson
- Robert Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxide-capped titanium silicide formation
- Patent number 5,326,724
- Issue date Jul 5, 1994
- Texas Instruments Incorporated
- Che-Chia Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Refractory metal capped low resistivity metal conductor lines and vias
- Patent number 5,300,813
- Issue date Apr 5, 1994
- International Business Machines Corporation
- Rajiv V. Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a CMOS semiconductor devices
- Patent number 5,273,914
- Issue date Dec 28, 1993
- Matsushita Electric Industrial Co., Ltd.
- Akio Miyajima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabricating a semiconductor device with strained Si.sub.1-x Ge.sub....
- Patent number 5,256,550
- Issue date Oct 26, 1993
- Hewlett-Packard Company
- Stephen Laderman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for inhibiting outgrowth of silicide in self-aligned silici...
- Patent number 5,196,360
- Issue date Mar 23, 1993
- Micron Technologies, Inc.
- Trung T. Doan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming isolated regions of oxide
- Patent number 5,192,707
- Issue date Mar 9, 1993
- SGS-Thomson Microelectronics, Inc.
- Robert Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a semiconductor device including a protective...
- Patent number 5,134,093
- Issue date Jul 28, 1992
- Matsushita Electric Industrial Co., Ltd.
- Teruhito Onishi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of rendering the impurity concentration of a semiconductor w...
- Patent number 5,130,261
- Issue date Jul 14, 1992
- Kabushiki Kaisha Toshiba
- Yoshikazu Usuki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diffusion using a solid state source
- Patent number 5,126,281
- Issue date Jun 30, 1992
- Hewlett-Packard Company
- Kent A. W. Carey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor processing with silicon cap over Si.sub.1-x Ge.sub.x...
- Patent number 5,084,411
- Issue date Jan 28, 1992
- Hewlett-Packard Company
- Stephen Laderman
- H01 - BASIC ELECTRIC ELEMENTS

Capping layer

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Refractory metal capped low resistivity metal conductor lines and v...

Refractory metal capped low resistivity metal conductor lines and vias

Refractory metal capped low resistivity metal conductor lines and vias

Method of manufacturing a semiconductor device and semiconductor de...

Refractory metal capped low resistivity metal conductor lines and vias

Semiconductor device and method of manufacturing the same

Refractory metal capped low resistivity metal conductor lines and vias

Process for forming titanium silicide local interconnect

Method of diffusing a metal through a silver electrode to form a pr...

Multilayer aluminum wiring in semiconductor IC

Process for forming titanium silicide local interconnect

Method to prevent silicide bubble in the VLSI process

Method of fabricating a complementary heterojunction FET

Refractory metal capped low resistivity metal conductor lines and vias

Refractory metal capped low resistivity metal conductor lines and v...

Method of forming multilayer aluminum wiring in semiconductor IC

Method of manufacturing a semiconductor device isolated by a trench

Method of manufacturing a semiconductor device, in which a metal co...

Complementary heterojunction device

Method of forming isolated regions of oxide

Oxide-capped titanium silicide formation

Refractory metal capped low resistivity metal conductor lines and vias

Method of fabricating a CMOS semiconductor devices

Fabricating a semiconductor device with strained Si.sub.1-x Ge.sub....

Methods for inhibiting outgrowth of silicide in self-aligned silici...

Method of forming isolated regions of oxide

Method of fabricating a semiconductor device including a protective...

Method of rendering the impurity concentration of a semiconductor w...

Diffusion using a solid state source

Semiconductor processing with silicon cap over Si.sub.1-x Ge.sub.x...