Clock circuits aspects

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CPC
G01R31/31727

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/31727Clock circuits aspects

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Method and circuit for performing error detection on a clock gated...
- Patent number 12,229,002
- Issue date Feb 18, 2025
- Imagination Technologies Limited
- Faizan Nazar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock shaper circuit for transition fault testing
- Patent number 12,216,160
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Wilson Pradeep
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock gating for power reduction during testing
- Patent number 12,210,058
- Issue date Jan 28, 2025
- MARVELL ASIA PTE. LTD.
- Sreekanth G. Pai
- G01 - MEASURING TESTING
Information Patent Grant
Device access port selection
- Patent number 12,210,060
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Test element group and test method
- Patent number 12,210,059
- Issue date Jan 28, 2025
- Samsung Electronics Co., Ltd.
- Jeongha Kim
- G01 - MEASURING TESTING
Information Patent Grant
Test-time optimization with few slow scan pads
- Patent number 12,203,985
- Issue date Jan 21, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Oscillation period detection circuit and method, and semiconductor...
- Patent number 12,188,981
- Issue date Jan 7, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Zhiqiang Zhang
- G01 - MEASURING TESTING
Information Patent Grant
Test method for delay circuit and test circuitry
- Patent number 12,188,982
- Issue date Jan 7, 2025
- Realtek Semiconductor Corp.
- Kuo-Wei Chi
- G01 - MEASURING TESTING
Information Patent Grant
Test access port with address and command capability
- Patent number 12,188,980
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Frequency-detecting circuit, duty-cycle corrector, and electronic d...
- Patent number 12,184,287
- Issue date Dec 31, 2024
- GigaDevice Semiconductor Inc.
- Menghai Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
At-speed test access port operations
- Patent number 12,181,521
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data correction and phase optimization in high-speed receivers
- Patent number 12,181,523
- Issue date Dec 31, 2024
- Diodes Incorporated
- Yu-Wei Lin
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for fault detection and reporting through seria...
- Patent number 12,169,218
- Issue date Dec 17, 2024
- Maxim Integrated Products, Inc.
- Ling Liu
- G01 - MEASURING TESTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Time-to-digital converter circuit with self-testing function
- Patent number 12,164,002
- Issue date Dec 10, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- John Kevin Moore
- G04 - HOROLOGY
Information Patent Grant
Electronic device for self-testing period of clock signal and monit...
- Patent number 12,153,089
- Issue date Nov 26, 2024
- Richtek Technology Corporation
- Fu-Shiang Lai
- G01 - MEASURING TESTING
Information Patent Grant
Electronic circuit and method of error correction
- Patent number 12,153,088
- Issue date Nov 26, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chia-Chun Liao
- G01 - MEASURING TESTING
Information Patent Grant
Clock gating circuits and methods for dual-edge-triggered applications
- Patent number 12,146,912
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,146,909
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface to full and reduced pin JTAG devices
- Patent number 12,130,328
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
SOC-oriented concurrent test system for multiple clock domains and...
- Patent number 12,130,718
- Issue date Oct 29, 2024
- Macrotest Semiconductor Inc.
- Guoliang Mao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with timing correction circuitry
- Patent number 12,123,911
- Issue date Oct 22, 2024
- NXP USA, INC.
- Shilpa Gupta
- G01 - MEASURING TESTING
Information Patent Grant
Loopback testing of integrated circuits
- Patent number 12,123,908
- Issue date Oct 22, 2024
- PROTEANTECS LTD.
- Eyal Fayneh
- G01 - MEASURING TESTING
Information Patent Grant
Scan frame based test access mechanisms
- Patent number 12,117,490
- Issue date Oct 15, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Multiple clock and clock cycle selection for x-tolerant logic built...
- Patent number 12,117,488
- Issue date Oct 15, 2024
- Synopsys, Inc.
- Peter Wohl
- G01 - MEASURING TESTING
Information Patent Grant
Device and method for measuring characteristics of a wafer
- Patent number 12,117,489
- Issue date Oct 15, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Yung-Shun Chen
- G01 - MEASURING TESTING
Information Patent Grant
Testing system and testing method
- Patent number 12,111,353
- Issue date Oct 8, 2024
- Realtek Semiconductor Corporation
- Shih-Hsuan Chiu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Detection circuit of clock anomaly and method, clock circuit, chip...
- Patent number 12,111,354
- Issue date Oct 8, 2024
- SUTENG INNOVATION TECHNOLOGY CO., LTD.
- Yumin Liao
- G01 - MEASURING TESTING
Information Patent Grant
Electronic device and phase detector
- Patent number 12,099,089
- Issue date Sep 24, 2024
- NANYA TECHNOLOGY CORPORATION
- Wu-Der Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for transferring data from one clock domain to another
- Patent number 12,092,688
- Issue date Sep 17, 2024
- Advantest Corporation
- Andreas Beermann
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
- Publication number 20250052811
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
DEVICE, METHOD AND SYSTEM FOR IN-FIELD LANE TESTING AND REPAIR WITH...
- Publication number 20250052809
- Publication date Feb 13, 2025
- Intel Corporation
- Fei Su
- G01 - MEASURING TESTING
Information Patent Application
TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS
- Publication number 20250027994
- Publication date Jan 23, 2025
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
- Publication number 20250027995
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
FULLY DIGITAL DOMAIN INTEGRATED FREQUENCY MONITOR
- Publication number 20250012857
- Publication date Jan 9, 2025
- NVIDIA Corporation
- Ofek Abadi
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240402247
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DETECTING FAULTS IN INTEGRATED CIRCUITS
- Publication number 20240393391
- Publication date Nov 28, 2024
- NXP B.V.
- Jorge Ernesto Perez Chamorro
- G01 - MEASURING TESTING
Information Patent Application
CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION
- Publication number 20240385241
- Publication date Nov 21, 2024
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION
- Publication number 20240385242
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- CHIA-CHUN LIAO
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20240385244
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
DEVICE FOR MEASURING FREQUENCY RESPONSE OF A WAFER
- Publication number 20240369627
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- YUNG-SHUN CHEN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
- Publication number 20240361384
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
Machine Learning Control of Clock Drift
- Publication number 20240345161
- Publication date Oct 17, 2024
- Richard Maiden
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT WITH TIMING CORRECTION CIRCUITRY
- Publication number 20240345163
- Publication date Oct 17, 2024
- NXP USA, Inc.
- Shilpa Gupta
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANG...
- Publication number 20240337690
- Publication date Oct 10, 2024
- NVIDIA Corporation
- Kedar Rajpathak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER
- Publication number 20240337691
- Publication date Oct 10, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT TESTING METHOD
- Publication number 20240329119
- Publication date Oct 3, 2024
- Realtek Semiconductor Corp.
- Yu-Chen Hsieh
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST METHOD FOR SEMICONDUCTOR...
- Publication number 20240329132
- Publication date Oct 3, 2024
- Kabushiki Kaisha Toshiba
- Tomoyuki Maekawa
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR CONTROLLING AT-SPEED TESTING OF INTEGRATED CI...
- Publication number 20240295602
- Publication date Sep 5, 2024
- NXP B.V.
- Chandan Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCURATE CLOCK EDGE CALIBRATION OVER PVT CORNERS
- Publication number 20240288831
- Publication date Aug 29, 2024
- Meta Platforms Technologies, LLC
- Sri Harsha Manjunath
- G01 - MEASURING TESTING
Information Patent Application
ACCURATE CLOCK CALIBRATION FOR DIE-TO-DIE (D2D) INTERFACES
- Publication number 20240288494
- Publication date Aug 29, 2024
- Meta Platforms Technologies, LLC
- Sri Harsha Manjunath
- G01 - MEASURING TESTING
Information Patent Application
Low-Frequency Oscillator Monitoring Circuit
- Publication number 20240280634
- Publication date Aug 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Brett Forejt
- G01 - MEASURING TESTING
Information Patent Application
Latchup Detector and Clock Loss Detector
- Publication number 20240248134
- Publication date Jul 25, 2024
- Omni Design Technologies, Inc.
- Manar Ibrahim El-Chammas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TIMING MARGIN SENSOR
- Publication number 20240250673
- Publication date Jul 25, 2024
- Movellus Circuits Incorporated
- Marcus Van Ierssel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK RECOVERY UNIT ADJUSTMENT
- Publication number 20240243896
- Publication date Jul 18, 2024
- KEYSIGHT TECHNOLOGIES, INC.
- Marlin E. Viss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Test device for testing on-chip clock controller having debug function
- Publication number 20240230757
- Publication date Jul 11, 2024
- REALTEK SEMICONDUCTOR CORPORATION
- SHENG-PING YUNG
- G01 - MEASURING TESTING
Information Patent Application
DETERMINATION DEVICE, TEST SYSTEM, AND GENERATION DEVICE
- Publication number 20240230759
- Publication date Jul 11, 2024
- KIOXIA Corporation
- Mikio SHIRAISHI
- G01 - MEASURING TESTING
Information Patent Application
DISPLAY DEVICE, PANEL DEFECT DETECTION CIRCUIT AND PANEL DEFECT DET...
- Publication number 20240219463
- Publication date Jul 4, 2024
- LG Display Co., Ltd.
- Sangyun KIM
- G01 - MEASURING TESTING
Information Patent Application
SOC-ORIENTED CONCURRENT TEST SYSTEM FOR MULTIPLE CLOCK DOMAINS AND...
- Publication number 20240220381
- Publication date Jul 4, 2024
- Macrotest Semiconductor Inc.
- Guoliang Mao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
- Publication number 20240210473
- Publication date Jun 27, 2024
- Samsung Electronics Co., Ltd.
- Jangmok Yoo
- G06 - COMPUTING CALCULATING COUNTING

Clock circuits aspects

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method and circuit for performing error detection on a clock gated...

Clock shaper circuit for transition fault testing

Clock gating for power reduction during testing

Device access port selection

Test element group and test method

Test-time optimization with few slow scan pads

Oscillation period detection circuit and method, and semiconductor...

Test method for delay circuit and test circuitry

Test access port with address and command capability

Frequency-detecting circuit, duty-cycle corrector, and electronic d...

At-speed test access port operations

Data correction and phase optimization in high-speed receivers

Systems and methods for fault detection and reporting through seria...

3D tap and scan port architectures

Time-to-digital converter circuit with self-testing function

Electronic device for self-testing period of clock signal and monit...

Electronic circuit and method of error correction

Clock gating circuits and methods for dual-edge-triggered applications

Selectable JTAG or trace access with data store and output

Interface to full and reduced pin JTAG devices

SOC-oriented concurrent test system for multiple clock domains and...

Integrated circuit with timing correction circuitry

Loopback testing of integrated circuits

Scan frame based test access mechanisms

Multiple clock and clock cycle selection for x-tolerant logic built...

Device and method for measuring characteristics of a wafer

Testing system and testing method

Detection circuit of clock anomaly and method, clock circuit, chip...

Electronic device and phase detector

Circuit for transferring data from one clock domain to another

Patents Applicationslast 30 patents

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

DEVICE, METHOD AND SYSTEM FOR IN-FIELD LANE TESTING AND REPAIR WITH...

TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS

FULLY DIGITAL DOMAIN INTEGRATED FREQUENCY MONITOR

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

SYSTEM AND METHOD FOR DETECTING FAULTS IN INTEGRATED CIRCUITS

CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION

ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION

ADDRESSABLE TEST ACCESS PORT

DEVICE FOR MEASURING FREQUENCY RESPONSE OF A WAFER

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS

Machine Learning Control of Clock Drift

INTEGRATED CIRCUIT WITH TIMING CORRECTION CIRCUITRY

LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANG...

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER

INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT TESTING METHOD

SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST METHOD FOR SEMICONDUCTOR...

SYSTEM AND METHOD FOR CONTROLLING AT-SPEED TESTING OF INTEGRATED CI...

ACCURATE CLOCK EDGE CALIBRATION OVER PVT CORNERS

ACCURATE CLOCK CALIBRATION FOR DIE-TO-DIE (D2D) INTERFACES

Low-Frequency Oscillator Monitoring Circuit

Latchup Detector and Clock Loss Detector

TIMING MARGIN SENSOR

CLOCK RECOVERY UNIT ADJUSTMENT

Test device for testing on-chip clock controller having debug function

DETERMINATION DEVICE, TEST SYSTEM, AND GENERATION DEVICE

DISPLAY DEVICE, PANEL DEFECT DETECTION CIRCUIT AND PANEL DEFECT DET...

SOC-ORIENTED CONCURRENT TEST SYSTEM FOR MULTIPLE CLOCK DOMAINS AND...

SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME