covering only portions of the surface to be connected

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H01L2224/06164

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/06164covering only portions of the surface to be connected

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Power island segmentation for selective bond-out
- Patent number 11,211,329
- Issue date Dec 28, 2021
- Kioxia Corporation
- Benjamin Kerr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power island segmentation for selective bond-out
- Patent number 10,629,533
- Issue date Apr 21, 2020
- TOSHIBA MEMORY CORPORATION
- Benjamin Kerr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit (IC) die attached between an offset lead frame d...
- Patent number 10,553,524
- Issue date Feb 4, 2020
- Microchip Technology Incorporated
- Man Kit Lam
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Packaged semiconductor device with interior polygonal pads
- Patent number 10,056,343
- Issue date Aug 21, 2018
- Nexperia B.V.
- Roelf A. J. Groenhuis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method for manufacturing the same
- Patent number 9,754,865
- Issue date Sep 5, 2017
- Renesas Electronics Corporation
- Takanori Yamashita
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Semiconductor package structure including die and substrate electri...
- Patent number 9,748,196
- Issue date Aug 29, 2017
- Advanced Semiconductor Engineering, Inc.
- Jen-Kuang Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stub minimization for assemblies without wirebonds to package subst...
- Patent number 9,679,838
- Issue date Jun 13, 2017
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor circuit device, electronic device, electronic apparat...
- Patent number 9,484,857
- Issue date Nov 1, 2016
- Seiko Epson Corporation
- Yosuke Itasaka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stub minimization for assemblies without wirebonds to package subst...
- Patent number 9,373,565
- Issue date Jun 21, 2016
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Stub minimization with terminal grids offset from center of package
- Patent number 9,214,455
- Issue date Dec 15, 2015
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Stub minimization with terminal grids offset from center of package
- Patent number 8,917,532
- Issue date Dec 23, 2014
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Stub minimization for assemblies without wirebonds to package subst...
- Patent number 8,629,545
- Issue date Jan 14, 2014
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Stub minimization for assemblies without wirebonds to package subst...
- Patent number 8,610,260
- Issue date Dec 17, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for packaging ultra-thin chip with solder ball thermo-compre...
- Patent number 8,563,417
- Issue date Oct 22, 2013
- Alpha & Omega Semiconductor, Inc.
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stub minimization for assemblies without wirebonds to package subst...
- Patent number 8,525,327
- Issue date Sep 3, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit substrate and method of manufacturing same
- Patent number 8,508,046
- Issue date Aug 13, 2013
- Disco Corporation
- Masao Sakuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strain-compensating fill patterns for controlling semiconductor chi...
- Patent number 8,441,131
- Issue date May 14, 2013
- GLOBALFOUNDRIES Inc.
- Vivian W. Ryan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mixed analog and digital integrated circuits
- Patent number 6,472,747
- Issue date Oct 29, 2002
- QUALCOMM Incorporated
- Seyfollah Bazarjani
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
POWER ISLAND SEGMENTATION FOR SELECTIVE BOND-OUT
- Publication number 20200227353
- Publication date Jul 16, 2020
- Toshiba Memory Corporation
- Benjamin Kerr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER ISLAND SEGMENTATION FOR SELECTIVE BOND-OUT
- Publication number 20190287906
- Publication date Sep 19, 2019
- Toshiba Memory Corporation
- Benjamin Kerr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20170323848
- Publication date Nov 9, 2017
- RENESAS ELECTRONICS CORPORATION
- Takanori Yamashita
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED SEMICONDUCTOR DEVICE WITH INTERIOR POLYGONAL PADS
- Publication number 20160118357
- Publication date Apr 28, 2016
- NXP B.V.
- Roelf A.J. Groenhuis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE STRUCTURE
- Publication number 20160079157
- Publication date Mar 17, 2016
- ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Jen-Kuang FANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20140374890
- Publication date Dec 25, 2014
- Renesas Electronics Corporation
- Takanori Yamashita
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...
- Publication number 20140103535
- Publication date Apr 17, 2014
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor Package and Methods of Formation Thereof
- Publication number 20130292684
- Publication date Nov 7, 2013
- INFINEON TECHNOLOGIES AG
- Ivan Nikitin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PACKAGING ULTRA-THIN CHIP WITH SOLDER BALL THERMO-COMPRE...
- Publication number 20130130443
- Publication date May 23, 2013
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...
- Publication number 20130082375
- Publication date Apr 4, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Application
STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...
- Publication number 20130082389
- Publication date Apr 4, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Application
STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...
- Publication number 20130083582
- Publication date Apr 4, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Application
STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE
- Publication number 20130083584
- Publication date Apr 4, 2013
- Invensas Corporation
- Richard Dewitt Crisp
- G11 - INFORMATION STORAGE
Information Patent Application
Strain-Compensating Fill Patterns for Controlling Semiconductor Chi...
- Publication number 20130062775
- Publication date Mar 14, 2013
- GLOBALFOUNDRIES INC.
- Vivian W. Ryan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuit substrate and method of manufacturing same
- Publication number 20120193799
- Publication date Aug 2, 2012
- SKLink Co., Ltd.
- Masao SAKUMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Package with Reduced On-Resistance and Top Metal Spre...
- Publication number 20120175688
- Publication date Jul 12, 2012
- INTERNATIONAL RECTIFIER CORPORATION
- Rupert Burbidge
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIXED ANALOG AND DIGITAL INTEGRATED CIRCUITS
- Publication number 20020121679
- Publication date Sep 5, 2002
- Seyfollah Bazarjani
- G01 - MEASURING TESTING

covering only portions of the surface to be connected

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Power island segmentation for selective bond-out

Power island segmentation for selective bond-out

Integrated circuit (IC) die attached between an offset lead frame d...

Packaged semiconductor device with interior polygonal pads

Semiconductor device and method for manufacturing the same

Semiconductor package structure including die and substrate electri...

Stub minimization for assemblies without wirebonds to package subst...

Semiconductor circuit device, electronic device, electronic apparat...

Stub minimization for assemblies without wirebonds to package subst...

Stub minimization with terminal grids offset from center of package

Stub minimization with terminal grids offset from center of package

Stub minimization for assemblies without wirebonds to package subst...

Stub minimization for assemblies without wirebonds to package subst...

Method for packaging ultra-thin chip with solder ball thermo-compre...

Stub minimization for assemblies without wirebonds to package subst...

Circuit substrate and method of manufacturing same

Strain-compensating fill patterns for controlling semiconductor chi...

Mixed analog and digital integrated circuits

Patents Applicationslast 30 patents

POWER ISLAND SEGMENTATION FOR SELECTIVE BOND-OUT

POWER ISLAND SEGMENTATION FOR SELECTIVE BOND-OUT

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

PACKAGED SEMICONDUCTOR DEVICE WITH INTERIOR POLYGONAL PADS

SEMICONDUCTOR PACKAGE STRUCTURE

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...

Semiconductor Package and Methods of Formation Thereof

METHOD FOR PACKAGING ULTRA-THIN CHIP WITH SOLDER BALL THERMO-COMPRE...

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...

STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBST...

STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE

Strain-Compensating Fill Patterns for Controlling Semiconductor Chi...

Circuit substrate and method of manufacturing same

Semiconductor Package with Reduced On-Resistance and Top Metal Spre...

MIXED ANALOG AND DIGITAL INTEGRATED CIRCUITS