Patent Grant
9373565
The subject matter of the present application relates to microelectronic packages and assemblies incorporating microelectronic packages.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is contained in a package having external terminals which, in turn, are electrically connected to a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face.
In “flip chip” designs, the front face of the chip confronts the face of a package dielectric element, i.e., substrate of the package, and the contacts on the chip are bonded directly to contacts of the substrate by solder bumps or other connecting elements. In turn, the substrate can be bonded to a circuit panel through terminals overlying the face of the substrate. The “flip chip” design provides a relatively compact arrangement. In some cases, each package can be a “chip-scale package” which occupies an area of the circuit panel equal to or slightly larger than the area of the chip's front face, such as disclosed, for example, in certain embodiments of commonly-assigned U.S. Pat. Nos. 5,148,265; 5,148,266; and 5,679,977, the disclosures of which are incorporated herein by reference. Certain innovative mounting techniques offer compactness approaching or equal to that of conventional flip-chip bonding. Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/Os.” These I/Os must be interconnected with the I/Os of other chips. The interconnections should be short to minimize signal propagation delays. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines where increased performance and size reduction are needed.
Semiconductor chips containing memory storage arrays, particularly dynamic random access memory chips (DRAMs) and flash memory chips are commonly packaged in multiple-chip packages and assemblies. Each package has many electrical connections for carrying signals, power and ground between terminals, i.e., external connection points of the package, and the chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., which extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds which extending in both horizontal and vertical directions relative to the surface of the chip.
Conventional microelectronic packages can incorporate a microelectronic element predominantly having memory storage array function, i.e., one that embodies a greater number of active devices to provide memory storage array function than any other function. The microelectronic element may be or include a dynamic random access memory (DRAM) chip, or a stacked electrically interconnected assembly of such semiconductor chips. Typically, all of the terminals of such package are placed in sets of columns adjacent to one or more peripheral edges of a package substrate to which the microelectronic element is mounted. For example, in one conventional microelectronic package 12 seen in
In light of the foregoing, certain improvements in the positioning of terminals on microelectronic packages can be made in order to improve electrical performance, particularly in assemblies which include such packages and a circuit panel to which such packages can be mounted and electrically interconnected with one another.
A microelectronic package according to an aspect of the invention can include first and second microelectronic elements each embodying a greater number of active devices to provide memory storage array function than any other function. Each microelectronic element may have one or more columns of element contacts each column of element contacts extending in a first direction along a face of such microelectronic element. The package may include a substrate which has first and second opposed surfaces and first and second opposed edges extending between the first and second surfaces. The first surface may have first substrate contacts and second substrate contacts thereon. The first substrate contacts may face the element contacts of the first microelectronic element and be joined thereto, and the second substrate contacts may face the element contacts of the second microelectronic element and be joined thereto.
A plurality of terminals can be exposed at the second surface of the substrate and electrically connected with the first and second substrate contacts. The terminals can be disposed at positions within a plurality of parallel columns extending in the first direction along the second surface of the substrate and can be configured to connect the microelectronic package to at least one component external to the microelectronic package. The terminals can include first terminals disposed within at least one of the columns of terminals in a central region of the second surface of the substrate. The first terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within a microelectronic element of the first and second microelectronic elements.
In one example, the central region may have a width in a second direction along the second surface of the substrate transverse to the first direction. The width of the central region can be not more than three and one-half times a minimum pitch between any two adjacent columns of the parallel columns of the terminals. An axial plane extending in the first direction and centered relative to the columns of element contacts of the first and second microelectronic elements can extend in a third direction normal to the second surface of the substrate and may intersect the central region of the second surface.
In one example, the first terminals are configured to carry all of the address information usable by the circuitry within the package to determine the addressable memory location.
In one example, the first terminals may be configured to carry information that controls an operating mode of a microelectronic element of the first and second microelectronic elements.
In one example, the first terminals can be configured to carry all of the command signals transferred to the microelectronic package. The command signals can be write enable, row address strobe, and column address strobe signals.
In one example, the first terminals can be configured to carry clock signals transferred to the microelectronic package. The microelectronic package can be configured to use the clock signals to sample signals received at the terminals which carry the address information.
In one example, the first terminals can be configured to carry all of the bank address signals transferred to the microelectronic package.
In one example, the element contacts can include the one or more columns of element contacts, which can be first contacts containing a majority of the element contacts. The element contacts can further include second contacts on the face of at least one of the microelectronic elements which can be disposed adjacent to one or more edges of such face. The second contacts can be fewer than the number of first contacts in any one column thereof. The axial plane can be centered with respect to the first contacts, regardless of the positions of the second contacts.
In one example, each of the second contacts can be configured for at least one of: connection to at least one of a source of power or ground; or for contact with a probing device.
In one example, the first terminals can be disposed at positions within no more than four of the columns of terminals.
In one example, the substrate can include a dielectric element can have a coefficient of thermal expansion (“CTE”) in the plane of the dielectric element of less than 30 parts per million per degree Celsius (“ppm/° C.”).
In one example, the substrate can include an element which has a CTE of less than 12 ppm/° C.
In one example, the terminals can be configured for connecting the microelectronic package to an external component can be a circuit panel.
In one example, the faces of the first and second microelectronic elements can extend in a single plane parallel to the first surface of the substrate.
In one example, the microelectronic package may further include third and fourth microelectronic elements overlying the first surface of the substrate. Each of the third and fourth microelectronic elements may embody a greater number of active devices to provide memory storage array function than any other function. The third and fourth microelectronic elements each can have a face and element contacts on such face facing and joined to respective third and fourth substrate contacts on the first surface of the substrate.
In one example, at least some of the element contacts of the third and fourth microelectronic elements can be disposed at positions within one or more columns. Each column may include a plurality of the element contacts and extending along the face of the respective third or fourth microelectronic element. In one example, each column of element contacts of the third and fourth microelectronic elements may extend in the first direction, wherein the axial plane can be centered among all the columns of the first, second, third and fourth microelectronic elements.
In one example, the faces of the third and fourth microelectronic elements can extend in the single plane.
In one example, at least some of the element contacts of the third and fourth microelectronic elements can be disposed within one or more columns, and each such column may include a plurality of element contacts and extending along the face of the respective third or fourth microelectronic element in at least one direction transverse to the first direction.
In one example, the central region can be disposed within a rectangular area of the substrate beyond which none of the faces of the first, second, third and fourth microelectronic elements extends.
In one example, each of the first, second, third and fourth microelectronic elements may have two parallel first edges extending in the same direction as the columns of element contacts on the respective microelectronic element. Each such microelectronic element may have two parallel second edges extending in a direction transverse to the first edges of the respective microelectronic element. A plane containing either first edge of a respective microelectronic element and which extends in a direction normal to the face of the respective microelectronic element can intersect the first edge of another of the microelectronic elements.
In one example, the plane containing either first edge of the respective microelectronic element can interest the first edge of only one of the other microelectronic elements.
A microelectronic package according to an aspect of the invention can include first and second microelectronic elements each embodying a greater number of active devices to provide memory storage array function than any other function. Each microelectronic element can have one or more columns of element contacts. Each such column of element contacts may extend in a first direction along a face of such microelectronic element. A substrate can have first and second opposed surfaces and first and second opposed edges extending between the first and second surfaces. The first surface can have first substrate contacts and second substrate contacts thereon. The first substrate contacts can face the element contacts of the first microelectronic element and be joined thereto. The second substrate contacts can face the element contacts of the second microelectronic element and be joined thereto.
A plurality of terminals can be exposed at the second surface of the substrate and electrically connected with the first and second substrate contacts. The terminals can be disposed at positions within a plurality of parallel columns extending in the first direction along the second surface of the substrate and can be configured to connect the microelectronic package to at least one component external to the microelectronic package. The terminals can include first terminals disposed within at least one of the columns of terminals in a central region of the second surface. The first terminals can be configured to carry a majority of address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within a microelectronic element of the first and second microelectronic elements. The central region may have a width in a second direction along the second surface of the substrate transverse to the first direction which is not more than three and one-half times a minimum pitch between any two adjacent columns of the parallel columns of the terminals. An axial plane extending in the first direction and centered relative to the columns of element contacts of the first and second microelectronic elements can extend in a third direction normal to the second surface of the substrate and can intersect the central region of the second surface.
In one example, the first terminals can be configured to carry at least three quarters of the address information usable by the circuitry within the package to determine the addressable memory location.
A microelectronic package according to an embodiment of the invention can include a microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function. The microelectronic element can have one or more columns of element contacts each column extending in a first direction along a face of the microelectronic element, such that an axial plane extending in a direction normal to the face of the microelectronic element intersects the face of the microelectronic element along a line extending in the first direction and centered relative to the one or more columns of element contacts. The microelectronic package further includes packaging structure, such as a dielectric layer having a surface overlying the face of the microelectronic element and facing away from the face of the microelectronic element. A plurality of terminals can be exposed at the surface of the dielectric layer, at least some of the terminals which can be electrically connected with the element contacts through traces extending along the dielectric layer and metallized vias extending from the traces and contacting the element contacts. The terminals can be disposed at positions within a plurality of parallel columns and can be configured for connecting the microelectronic package to at least one component external to the microelectronic package. The terminals can include first terminals disposed within at least one column in the central region. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The central region can be not wider than three and one-half times a minimum pitch between any two adjacent columns of the terminals, and the axial plane may intersect the central region.
In one example, the first terminals can be configured to carry all of the address information usable by the circuitry within the package to determine the addressable memory location.
In one example, the first terminals can be configured to carry information that controls an operating mode of the microelectronic element.
In one example, the first terminals can be configured to carry all of the command signals transferred to the microelectronic package, the command signals can be write enable, row address strobe, and column address strobe signals.
In one example, the first terminals can be configured to carry clock signals transferred to the microelectronic package, each microelectronic package can be configured to use the clock signals to sample signals received at the terminals which carry the address information.
In one example, the first terminals can be configured to carry all of the bank address signals transferred to the microelectronic package.
In one example, the terminals can be configured for connecting the microelectronic package to an external component can be a circuit panel.
In view of the illustrative conventional microelectronic package 12 described relative to
Improvements can be made particularly for use of a microelectronic package when provided in an assembly such as shown in
The circuit panel 34 electrically interconnects the terminals of the respective packages 12A, 12B using local interconnect wiring that appears similar to a crisscross or “shoelace” pattern in which a terminal labeled “1” near one edge of package 12A connects through the circuit panel 34 to a terminal labeled “1” of package 12B near the same edge 16 of package 12B. However, the edge 16 of package 12B as assembled to circuit panel 34 is far from the edge 16 of package 12A.
Connections through the circuit panel between terminals on each package, e.g., package 12A, to the corresponding terminals on the package mounted opposite thereto, i.e., package 12B, are fairly long. As further seen in
In some cases, the lengths of the circuit panel wiring required to connect the terminals of such oppositely mounted microelectronic packages may not severely impact the electrical performance of the assembly. However, when the signal carried by the connected pair of terminals on the packages 12A, 12B is a signal from a bus 36 used to carry address information or other information such as clock information for sampling the address information which is common to operation of the memory storage array function of a plurality of packages connected to the circuit panel, the inventors recognize that the wiring length of the stubs extending from the bus 36 to the terminals on each package may significantly affect performance. When the interconnecting wiring is relatively long, a more severe impact occurs, which can increase settling time, ringing, jitter, or intersymbol interference for a transmitted signal to an unacceptable degree.
In a particular embodiment, the bus 36 used to carry address information can be a command-address bus 36 configured to carry command information, address information, bank address information and clock information. In a specific implementation, the command information can be transmitted as command signals on respective signal conductors on the circuit panel. It is also possible for the address information to be transmitted as address signals on respective signal conductors, as it is also possible for the bank address information to be transmitted as bank address signals on respective signal conductors, and it is also possible for the clock information to be transmitted as clock signals on respective signal conductors. In a specific implementation of a microelectronic element which has a memory storage array such as a DRAM chip, the command signals which can be carried by the bus 36 can be write enable, row address strobe and column address strobe, and the clock signals which can be carried by the bus 36 can be clock signals used at least for sampling address signals carried by the bus 36.
Accordingly, certain embodiments of the invention described herein provide a microelectronic package configured so as to permit the lengths of stubs on a circuit panel to be reduced when first and second such packages are mounted opposite one another on opposite surfaces of a circuit panel, e.g., a circuit board, module board or card, or flexible circuit panel. Assemblies which incorporate first and second microelectronic packages electrically connected to a circuit panel at locations of the circuit panel opposite from one another can have significantly reduced stub lengths between the respective packages. Reducing the stub lengths within such assemblies can improve electrical performance, such as by reducing one or more of settling time, ringing, jitter, or intersymbol interference, among others. Moreover, it may be possible to obtain other benefits as well, such as simplifying the structure of the circuit panel or reducing the complexity and cost of designing or manufacturing the circuit panel, or for both designing and manufacturing the circuit panel.
Thus, a microelectronic package 100 according to an embodiment of the invention is illustrated in
Thus, a microelectronic package 100 according to an embodiment of the invention is illustrated in
The terminals can be disposed at locations within a plurality of parallel columns 104A, 104B, 106A and 106B on a surface 110 of the substrate. In the example shown in
As described above, the second terminals 106A, 106B may be disposed at positions within one or more of first and second peripheral regions 114A, 114B of the substrate surface 110. The first and second peripheral regions may in some cases be adjacent to first and second opposed edges 116, 118 of the surface 110, as seen in
In a particular example, when the microelectronic element includes or is a DRAM semiconductor chip, the terminals in the central region can be configured to carry address information transferred to the microelectronic package which is usable by circuitry within the package, e.g., by row address and column address decoders, and bank selection circuitry, if present, to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Typically, when the microelectronic element includes a DRAM chip, the address information in one embodiment can include all address information transferred to the package from a component external to the package, e.g., a circuit panel, which is used for determining a random access addressable memory location within a memory storage array within the microelectronic package for read access thereto, or for either read or write access thereto.
In a specific implementation, such as when the microelectronic element is of a type which receives address signals from a command-address bus on the circuit panel, the first terminals may be configured to carry address signals, bank address signals, certain command signals, and clock signals which are clocks used for sampling the address signals. While the clock signals can be of various types, in one embodiment, the clock signals carried by these terminals can be one or more pairs of differential clock signals received as differential or true and complement clock signals. The “command signals” in this case can be a write enable signal, a row address strobe signal, and a column address strobe signal utilized by a microelectronic element within the microelectronic package. For example, in a particular example as seen in
As seen in the sectional view of
In the example seen in
As further shown in
Thus, the contacts of the microelectronic element may include the one or more columns of contacts 138, 139 being first contacts and containing a majority of the contacts. The contacts of the microelectronic element may further include second contacts 192 on the face of the microelectronic element disposed adjacent to one or more edges of the face. The second contacts 192 are fewer than the number of first contacts in any one column thereof. In a particular example, each of the second contacts may be configured to be connected to one of a source of power, a ground, or be configured for connection to a probing device. In the completed package 100, these contacts may be without electrical connections with the substrate 102, or in some cases may be electrically connected only to corresponding power or ground conductors on the substrate. In such example, the intersection of the axial plane 140 with the face 134 of the microelectronic element 130 can be centered with respect to the columns of the first contacts, e.g., columns 138, 139 as seen in
Referring to
As further seen in
As further shown in
As further seen in
The minimum pitch is in a direction 143 perpendicular to the direction 142 in which the terminals in a particular column, e.g., column 104A are arranged. In the example shown in
The first and second microelectronic packages 100A, 100B can be mounted to corresponding panel contacts 360, 362 exposed at the first and second surfaces 350, 352 of the circuit panel 354. In the example shown in
In a particular example, the grids may be aligned with one another in the x and y directions such that at least some of the first terminals on the first and second microelectronic packages are coincident with one another. As used herein, when the first terminals of packages at opposite surfaces of a circuit panel are “coincident” with one another, the alignment can be within customary manufacturing tolerances or can be within a tolerance of less than one-half of one ball pitch of one another in x and y orthogonal directions parallel to the first and second circuit panel surfaces, the ball pitch being as described above.
Wiring within the circuit panel 354 electrically connects the terminals 104A of package 100A with terminals 104A of package 100B, as shown. The wiring that forms the electrical connections is shown schematically by the dashed line 320 in
Further, in a particular example as shown in
Therefore, the electrical lengths of stubs on the circuit panel 354 which electrically connect a first terminal 104A of the first package 100A with the corresponding first terminal 104A on the second package 100B can be less than seven times a minimum pitch of the first terminals on each package, for example, less than seven times the pitch 150 between columns 104A, 104B of first terminals in
The reductions in the lengths of these electrical connections can reduce stub lengths in the circuit panel and the assembly, which can help improve the electrical performance, such as reducing settling time, ringing, jitter, or intersymbol interference, among others, for the above-noted signals which are carried by the first terminals and which are transferred to microelectronic elements in both the first and second packages.
Moreover, it may be possible to obtain other benefits as well, such as simplifying the structure of the circuit panel or reducing the complexity and cost of designing or manufacturing the circuit panel. That is, connections on the circuit panel may require fewer layers of wiring to interconnect the first terminals of each package to the bus on the circuit panel, such as the above-discussed bus which carries address information or a command-address bus.
In addition, the number of global routing layers of conductors, i.e., wiring extending in at least one direction generally parallel to a surface of the circuit panel, which is required to route signals from the above-noted signals carried by the first terminals, e.g., address information or command-address bus signals can sometimes be reduced. For example, the number of such global routing layers between a connection site where a first pair of microelectronic packages 100A, 100B is connected and a different connection site where at least one other microelectronic package is connected, e.g., between connection sites II and III (
In an exemplary embodiment, the microelectronic assembly 354 can have a second microelectronic element 358 that can include a semiconductor chip configured to perform buffering of at least some signals transferred to the microelectronic packages 100A, 100B of the assembly 354. In a particular embodiment, the second microelectronic element can be configured predominantly to perform a logic function, such as a solid state drive controller, and one or more of the microelectronic elements 358 in the microelectronic packages 100A and 100B can each include memory storage elements such as nonvolatile flash memory. In one example, the second microelectronic element 358 can include a special purpose processor that is configured to relieve a central processing unit of a system such as the system 1500 (
In a particular embodiment, the first terminals 104 of the microelectronic package can be configured to carry information that controls an operating mode of the microelectronic element 101. More specifically, the first terminals can be configured to carry all of a particular set of command signals and/or clock signals transferred to the microelectronic package 100. In one embodiment, the first terminals 104 can be configured to carry all of the command signals, address signals, bank address signals, and clock signals transferred to the microelectronic package 100 from an external component, wherein the command signals include row address strobe, column address strobe and write enable. In such embodiment, the first chip can be configured to regenerate the information that controls the operating mode. Alternatively, or in addition thereto, the first chip can be configured to partially or fully decode the information that controls the operating mode of the microelectronic element. In such embodiment, each second chip may or may not be configured to fully decode one or more of address information, command information, or information that controls an operating mode of the microelectronic element.
Microelectronic packages having other arrangements of terminals thereon can be provided. For example, in the microelectronic package 400 illustrated in
In the microelectronic package 500 illustrated in
In the particular example seen in
As further seen in
In the microelectronic package 600 seen in
Alternatively, in another example, the one or more second semiconductor chips 634 may embody a greater number of active devices to provide memory storage array function than any other function, but the first semiconductor chip 632 may be a different type of chip. In this case, the first semiconductor chip 632 can be configured, e.g., designed, constructed, or set up, to buffer signals, i.e., regenerate signals received at the terminals for transfer to the one or more second semiconductor chips 634, or to regenerate signals received from one or more of the second semiconductor chips 634 for transfer to the terminals, or to regenerate signals being transferred in both directions from the terminals to the one or more second semiconductor chips 634; and from the one or more semiconductor chips to the terminals of the microelectronic package.
Alternatively or in addition to regenerating signals as described above, in one example, the first chip in such a composite microelectronic element can be configured to partially or fully decode the information that controls the operating mode of the microelectronic element. In a particular example, the first semiconductor chip in such composite microelectronic element can be configured to partially or fully decode at least one of address information or command information received at the terminals, such as at the first terminals. The first chip can then output the result of such partial or full decoding for transfer to the one or more second semiconductor chips 634.
In a particular example, the first semiconductor chip can be configured to buffer the address information, or in one example, the command signals, address signals and clock signals which are transferred to the one or more second semiconductor chips. For example, the first semiconductor chip 632 can be a buffer chip which embodies a greater number of active devices to provide a buffering function in transferring signals to other devices, e.g., to the one or more second semiconductor chips 634, than for any other function. Then, the one or more second semiconductor chips may be reduced function chips which have memory storage arrays but which can omit circuitry common to DRAM chips, such as buffer circuitry, decoders or predecoders or wordline drivers, among others. In that case, the first chip 632 may function as a “master” chip in the stack and to control operations in each of the second semiconductor chips 634. In a particular example, the second semiconductor chips may be configured such that they are not capable of performing the buffering function. In that case, the stacked arrangement of the first and second semiconductor chips is configured such that the buffering function required in the microelectronic package can be performed by the first semiconductor chip, and cannot be performed by any of the second semiconductor chips in the stacked arrangement.
In any of the embodiments described herein, the one or more second semiconductor chips can be implemented in one or more of the following technologies: DRAM, NAND flash memory, RRAM (“resistive RAM” or “resistive random access memory”), phase-change memory (“PCM”), magnetoresistive random access memory, e.g. such as may embodiment tunnel junction devices, spin-torque RAM, or content-addressable memory, among others.
Signals which are regenerated by a first semiconductor chip 632 operating as a buffer element, which are then transferred to the one or more second semiconductor chips, can be routed through TSVs connected to internal circuitry, for example. As further seen in
In the example shown in
In one example, the semiconductor chips 962, 963A, and 963B may include memory storage arrays. As in the examples described above, such chips 962, 963A, and 963B may each incorporate circuits configured to buffer, e.g., temporarily store, data that is to be written to such chip, or data that is being read from such chip, or both. Alternatively, the chips 962, 963A, and 963B may be more limited in function and may need to be used together with at least one other chip that is configured to temporarily store data that is to be written to such chip or data that is being read from such chip, or both.
The semiconductor chip 964 can be electrically connected to terminals of the microelectronic package, e.g., to grids in which the first terminals 904 and the second terminals 906 are disposed, through electrically conductive structure, e.g., TSVs 972a and 972b (collectively TSVs 972), that connect to contacts exposed at the first surface 108 of the substrate 902. The electrically conductive structure, e.g., the TSVs 972, can electrically connect to the semiconductor chip 964 through contacts 938 on the chip 964 and through conductors (not shown) that extend along the face 943 of the chip 964, or along a confronting face 931 of the chip 963A, or along the faces 931, 943 of both of the chips 963A, 964. As indicated above, the semiconductor chip 964 may be configured to regenerate or at least partially decode signals or information that it receives through the conductive structure, e.g., the TSVs 972 such as TSVs 972a and 972b, and it may be configured to transfer the regenerated or at least partially decoded signals or information to other chips within the package such as to the chips 962, 963A, and 963B.
As further seen in
As further seen in
The microelectronic assembly 995 shown in
This and other embodiments incorporate more than one microelectronic element therein as described above. A multiple chip package can reduce the amount of area or space required to connect the chips therein to a circuit panel, e.g., printed wiring board to which the package may be electrically and mechanically connected through an array of terminals, such as a ball grid array, land grid array or pin grid array, among others. Such connection space is particularly limited in small or portable computing devices, e.g., handheld devices such as “smartphones” or tablets that typically combine the function of personal computers with wireless connectivity to the broader world. Multi-chip packages can be particularly useful for making large amounts of relatively inexpensive memory available to a system, such as, for example, advanced high performance dynamic random access memory (“DRAM”) chips, e.g., in DDR3 type DRAM chips and its follow-ons.
In certain cases, the amount of area of the circuit panel needed to connect the multi-chip package thereto can be reduced by providing common terminals on the package through which at least some signals travel on their way to or from two or more chips within the package. Thus, in the example illustrated in
As in the above-described embodiments, the central region 1112 of the substrate surface 1110 has a width 1154 that is not greater than three and one-half times a minimum pitch 1152 between any two adjacent columns of terminals 1142 on the package, where each of the two adjacent columns has a plurality of terminals therein.
An axial plane 1150 extending in a direction orthogonal to the faces of the microelectronic elements extends in the same first direction in which each column containing a plurality of element contacts extends and is centered among all the columns 1138 of the element contacts of the first and second microelectronic elements 1130, 1131. The axial plane intersects the central region of the substrate. Referring to
The first terminals 1242 of the microelectronic package can be disposed within columns in a central region 1254 having width no greater than three and one-half times the minimum pitch between columns of terminals, as described above. As further shown in
In like manner to that described above relative to
Also, as shown in
As further shown in
In one example, “X” can be a number 2n (2 to the power of n), wherein n is greater than or equal to 2, or X can be 8×N, N being two or more. Thus, in one example, X may be equal to the number of bits in a half-byte (4 bits), byte (8 bits), multiple bytes (8×N, N being two or more), a word (32 bits) or multiple words. In such way, in one example, when there is modulo-8 symmetry as shown in
It is important to note that, although not shown, the modulo number “X” can be a number other than 2n (2 to the power of n) and can be any number greater than two. Thus, the modulo number X upon which the symmetry is based can depend upon how many bits are present in a data size for which the package is constructed or configured. For example, when the data size is 10 bits instead of 8, then the signal assignments may have modulo-10 symmetry. It may even be the case that when the data size has an odd number of bits, the modulo number X can have such number.
As further seen in
In addition, as further seen in
Each of the variations and embodiments described above can be applied as well to the packages shown in
The structures discussed above can be utilized in construction of diverse electronic systems. For example, as shown in
Various features of the above-described embodiments of the invention can be combined in ways other than as specifically described above without departing from the scope or spirit of the invention. It is intended for the present disclosure to cover all such combinations and variations of embodiments of the invention described above.
The present application is a divisional of U.S. patent application Ser. No. 13/439,299, filed Apr. 4, 2012. Application Ser. No. 13/439,299 claims the benefit of U.S. Provisional Patent Applications 61/542,488, 61/542,495, and 61/542,553, each filed Oct. 3, 2011, and U.S. Provisional Patent Application 61/600,361 filed Feb. 17, 2012, the disclosures of all of which are hereby incorporated herein by reference.
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