Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric

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H01L2221/1031

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00

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H01L2221/1031Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric

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Patents Grantslast 30 patents

Information Patent Grant
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Information Patent Grant
Etch damage and ESL free dual damascene metal interconnect
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Information Patent Grant
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Information Patent Grant
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INTERCONNECTION STRUCTURE FOR PACKAGE AND FABRICATION METHOD THEREOF
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- H01 - BASIC ELECTRIC ELEMENTS

Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor arrangement and method of making

Etch damage and ESL free dual damascene metal interconnect

Semiconductor arrangement and method of making

Semiconductor device, fabrication method for a semiconductor device...

Interconnect structure and methods thereof

Semiconductor arrangement and method of making

Etch damage and ESL free dual damascene metal interconnect

Devices including conductive interconnect structures, related elect...

Method of forming interconnection structure

Semiconductor device, fabrication method for a semiconductor device...

Interconnect structure and method of forming the same

Via blocking layer

Conductive line system and process

Dual-damascene formation with dielectric spacer and thin liner

Selectively etched self-aligned via processes

Interconnect structure and method of forming the same

Semiconductor devices

Method for manufacturing interconnection

In-line protection from process induced dielectric damage

Semiconductor device, fabrication method for a semiconductor device...

Fabrication method of semiconductor substrate

Etch damage and ESL free dual damascene metal interconnect

Conductive line system and process

Semiconductor device having interconnect layer that includes dielec...

Semiconductor devices

Semiconductor device manufacturing method

Memory device and operation method thereof

Semiconductor device, fabrication method for a semiconductor device...

Air-gap assisted etch self-aligned dual Damascene

Semiconductor constructions

Patents Applicationslast 30 patents

SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING

INTERCONNECT STRUCTURE AND METHODS THEREOF

SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

INTERCONNECTION STRUCTURE WITH SIDEWALL PROTECTION LAYER

SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR A SEMICONDUCTOR DEVICE...

SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE INTERCONNECT STRUCTURES,...

INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

Conductive Line System and Process

SEMICONDUCTOR DEVICES

IN-LINE PROTECTION FROM PROCESS INDUCED DIELECTRIC DAMAGE

DUAL-DAMASCENE FORMATION WITH DIELECTRIC SPACER AND THIN LINER

SEMICONDUCTOR DEVICES

FIN-LIKE FIELD EFFECT TRANSISTOR DEVICE

SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR A SEMICONDUCTOR DEVICE...

INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME

VIA BLOCKING LAYER

FABRICATION METHOD OF SEMICONDUCTOR SUBSTRATE

MEMORY DEVICE AND OPERATION METHOD THEREOF

Conductive Line System and Process

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

VIA BLOCKING LAYER

Semiconductor Constructions

INTEGRATED CIRCUIT WITH A SIDEWALL LAYER AND AN ULTRA-THICK METAL L...

Conductive Line System and Process

Conductive Line System and Process

INTERCONNECTION STRUCTURE FOR PACKAGE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR DEVICE INCLUDING PASSIVATION LAYER ENCAPSULANT