Dual dielectric

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CPC
Y10S148/043

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YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10USPC classification Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10S148/00Metal treatment

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Y10S148/043Dual dielectric

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Patents Grantslast 30 patents

Information Patent Grant
CVD apparatus
- Patent number 6,520,189
- Issue date Feb 18, 2003
- Semiconductor Energy Laboratory Co., Ltd.
- Takashi Inushima
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Insulation layer structure and method for making the same
- Patent number 6,150,220
- Issue date Nov 21, 2000
- Hyundai Electronics Industries Co., Ltd.
- Yun-Jun Huh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a polysilicon TFT with a variable thicknes...
- Patent number 6,124,153
- Issue date Sep 26, 2000
- SamSung Electronics Co., Ltd.
- Joo-hyung Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CVD apparatus
- Patent number 6,013,338
- Issue date Jan 11, 2000
- Semiconductor Energy Laboratory Co., Ltd.
- Takashi Inushima
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Interconnect structure with an integrated low density dielectric
- Patent number 5,747,880
- Issue date May 5, 1998
- Texas Instruments Incorporated
- Robert H. Havemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making an interconnect structure with an integrated low d...
- Patent number 5,488,015
- Issue date Jan 30, 1996
- Texas Instruments Incorporated
- Robert H. Havemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating metallized substrates using an organic etch b...
- Patent number 5,474,956
- Issue date Dec 12, 1995
- Hughes Aircraft Company
- Philip A. Trask
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of controlling oxide thinning in an EPROM or flash memory array
- Patent number 5,397,725
- Issue date Mar 14, 1995
- National Semiconductor Corporation
- Graham R. Wolstenholme
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip interconnection having a breathable etch stop layer
- Patent number 5,371,047
- Issue date Dec 6, 1994
- International Business Machines Corporation
- Stephen E. Greco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for moisture sealing integrated circuits using silicon nitri...
- Patent number 5,294,295
- Issue date Mar 15, 1994
- VLSI Technology, Inc.
- Calvin T. Gabriel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for etching improved contact openings to peripheral circuit...
- Patent number 5,286,677
- Issue date Feb 15, 1994
- Industrial Technology Research Institute
- Kuo-Chang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming multilevel interconnection in a semiconductor de...
- Patent number 5,219,792
- Issue date Jun 15, 1993
- Samsung Electronics Co., Ltd.
- Jang-rae Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual dielectric field effect transistors for protected gate structu...
- Patent number 5,210,045
- Issue date May 11, 1993
- General Electric Company
- George E. Possin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for plugging defects in a dielectric layer of a semiconduct...
- Patent number 5,208,189
- Issue date May 4, 1993
- Motorola, Inc.
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing InP junction FETS and junction HEMTS using...
- Patent number 5,196,358
- Issue date Mar 23, 1993
- The United States of America as represented by the Secretary of the Navy
- John B. Boos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of filling a recess flat with a material by a bias ECR-CVD p...
- Patent number 5,182,221
- Issue date Jan 26, 1993
- Sony Corporation
- Junichi Sato
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned structure and process for DMOS transistor
- Patent number 5,171,705
- Issue date Dec 15, 1992
- Supertex, Inc.
- Benedict C. K. Choy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Suppression of water vapor absorption in glass encapsulation
- Patent number 5,094,984
- Issue date Mar 10, 1992
- Hewlett-Packard Company
- Charles C. Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication method of contact window in semiconductor device
- Patent number 5,073,510
- Issue date Dec 17, 1991
- Samsung Electronics Co., Ltd.
- Oh-Hyun Kwon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit interconnect having dual dielectric intermediate...
- Patent number 5,070,037
- Issue date Dec 3, 1991
- Delco Electronics Corporation
- Ronald K. Leisure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating self-aligned semiconductor devices
- Patent number 5,061,644
- Issue date Oct 29, 1991
- Honeywell Inc.
- Jerry Yue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a bipolar transistor
- Patent number 5,023,192
- Issue date Jun 11, 1991
- U.S. Philips Corporation
- Wilhelmus J. Josquin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing an intergrated circuit including steps for...
- Patent number 5,006,485
- Issue date Apr 9, 1991
- U.S. Philips Corporation
- Claudine Villalon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor planarization process for submicron devices
- Patent number 5,003,062
- Issue date Mar 26, 1991
- Taiwan Semiconductor Manufacturing Co.
- Daniel L. Yen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating III-V devices using a composite dielectric...
- Patent number 5,001,076
- Issue date Mar 19, 1991
- Vitesse Semiconductor Corporation
- James M. Mikkelson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned dielectric assisted planarization process
- Patent number 4,996,165
- Issue date Feb 26, 1991
- Rockwell International Corporation
- Mau-Chung F. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for producing a semiconductor device having a silicon oxyni...
- Patent number 4,980,307
- Issue date Dec 25, 1990
- Fujitsu Limited
- Takashi Ito
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for planarization of a semiconductor device prior to metalli...
- Patent number 4,966,865
- Issue date Oct 30, 1990
- Texas Instruments Incorporated
- Michael T. Welch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making a self aligned vertical field effect transistor...
- Patent number 4,960,723
- Issue date Oct 2, 1990
- Motorola, Inc.
- Robert B. Davies
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of depositing films using photo-CVD with chamber plasma clea...
- Patent number 4,950,624
- Issue date Aug 21, 1990
- Semiconductor Energy Laboratory Co., Ltd.
- Takashi Inuzima
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Patents Applicationslast 30 patents

Information Patent Application
CVD apparatus
- Publication number 20030140941
- Publication date Jul 31, 2003
- Semiconductor Energy Laboratory Co., Ltd.
- Takashi Inushima
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Dual dielectric

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

CVD apparatus

Insulation layer structure and method for making the same

Method for manufacturing a polysilicon TFT with a variable thicknes...

CVD apparatus

Interconnect structure with an integrated low density dielectric

Method of making an interconnect structure with an integrated low d...

Method of fabricating metallized substrates using an organic etch b...

Method of controlling oxide thinning in an EPROM or flash memory array

Chip interconnection having a breathable etch stop layer

Method for moisture sealing integrated circuits using silicon nitri...

Method for etching improved contact openings to peripheral circuit...

Method for forming multilevel interconnection in a semiconductor de...

Dual dielectric field effect transistors for protected gate structu...

Process for plugging defects in a dielectric layer of a semiconduct...

Method of manufacturing InP junction FETS and junction HEMTS using...

Method of filling a recess flat with a material by a bias ECR-CVD p...

Self-aligned structure and process for DMOS transistor

Suppression of water vapor absorption in glass encapsulation

Fabrication method of contact window in semiconductor device

Integrated circuit interconnect having dual dielectric intermediate...

Method for fabricating self-aligned semiconductor devices

Method of manufacturing a bipolar transistor

Method of manufacturing an intergrated circuit including steps for...

Semiconductor planarization process for submicron devices

Process for fabricating III-V devices using a composite dielectric...

Self-aligned dielectric assisted planarization process

Process for producing a semiconductor device having a silicon oxyni...

Method for planarization of a semiconductor device prior to metalli...

Process for making a self aligned vertical field effect transistor...

Method of depositing films using photo-CVD with chamber plasma clea...

Patents Applicationslast 30 patents

CVD apparatus