for combinational circuits

Industry

CPC
G01R31/318321

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318321for combinational circuits

Industries

Patents Grantslast 30 patents

Information Patent Grant
Integrating machine learning delay estimation in FPGA-based emulati...
- Patent number 12,140,628
- Issue date Nov 12, 2024
- Synopsys, Inc.
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan tree construction
- Patent number 12,092,691
- Issue date Sep 17, 2024
- Tsinghua University
- Can Xiang
- G01 - MEASURING TESTING
Information Patent Grant
Machine learning delay estimation for emulation systems
- Patent number 11,860,227
- Issue date Jan 2, 2024
- Synopsys, Inc.
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit having scan chains sequentially su...
- Patent number 11,519,963
- Issue date Dec 6, 2022
- Kioxia Corporation
- Masaki Ooiso
- G01 - MEASURING TESTING
Information Patent Grant
Testing device and testing method for testing a device under test
- Patent number 11,280,833
- Issue date Mar 22, 2022
- Rohde & Schwarz GmbH & Co. KG
- Stefan Schmidt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test response compaction scheme
- Patent number 10,416,226
- Issue date Sep 17, 2019
- GLOBALFOUNDRIES Inc.
- Jaidev Udyavar Shenoy
- G01 - MEASURING TESTING
Information Patent Grant
Method of fault tolerance in combinational circuits
- Patent number 10,013,296
- Issue date Jul 3, 2018
- King Fahd University of Petroleum & Minerals
- Aiman Helmi El-Maleh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for improved test controllability and observab...
- Patent number 7,882,454
- Issue date Feb 1, 2011
- International Business Machines Corporation
- Mary P Kusko
- G01 - MEASURING TESTING
Information Patent Grant
System and method for signature-based systematic condition detectio...
- Patent number 7,853,848
- Issue date Dec 14, 2010
- International Business Machines Corporation
- Rao H. Desineni
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for bit pattern learning and computer product
- Patent number 7,246,292
- Issue date Jul 17, 2007
- Fujitsu Limited
- Daisuke Maruyama
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for accelerated post-silicon testing and rando...
- Patent number 7,133,818
- Issue date Nov 7, 2006
- Sun Microsystems, Inc.
- Keith H. Bierman
- G01 - MEASURING TESTING
Information Patent Grant
Method of generating test pattern for integrated circuit
- Patent number 7,024,606
- Issue date Apr 4, 2006
- NEC Electronics Corporation
- Hisashi Yamauchi
- G01 - MEASURING TESTING
Information Patent Grant
Method for monitoring and improving integrated circuit fabrication...
- Patent number 7,020,860
- Issue date Mar 28, 2006
- Xilinx, Inc.
- Joe W. Zhao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits and methods for characterizing the speed performance of mu...
- Patent number 6,850,123
- Issue date Feb 1, 2005
- Xilinx, Inc.
- Himanshu J. Verma
- G01 - MEASURING TESTING
Information Patent Grant
Cell architecture to reduce customization in a semiconductor device
- Patent number 6,580,289
- Issue date Jun 17, 2003
- Viasic, Inc.
- William D. Cox
- G01 - MEASURING TESTING
Information Patent Grant
Fault propagation path estimating method, fault propagation path es...
- Patent number 6,560,738
- Issue date May 6, 2003
- NEC Electronics Corporation
- Kazuki Shigeta
- G01 - MEASURING TESTING
Information Patent Grant
Device and method for testing a semiconductor
- Patent number 6,405,336
- Issue date Jun 11, 2002
- NEC Corporation
- Akira Ohashi
- G01 - MEASURING TESTING
Information Patent Grant
Method of generating test patterns for a logic circuit, a system pe...
- Patent number 6,334,199
- Issue date Dec 25, 2001
- NEC Corporation
- Toshinobu Ono
- G01 - MEASURING TESTING
Information Patent Grant
Liquid crystal display driving device and liquid crystal inspection...
- Patent number 5,757,346
- Issue date May 26, 1998
- Casio Computer Co., Ltd.
- Hiroaki Mita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Output pin for selectively outputting one of a plurality of signals...
- Patent number 5,717,695
- Issue date Feb 10, 1998
- Silicon Graphics, Inc.
- Philip R. Manela
- G01 - MEASURING TESTING
Information Patent Grant
Built-in self tests for large multiplier, adder, or subtractor
- Patent number 5,600,658
- Issue date Feb 4, 1997
- National Semiconductor Corporation
- Fazal U. R. Qureshi
- G01 - MEASURING TESTING
Information Patent Grant
Testing VLSI circuits for defects
- Patent number 5,506,852
- Issue date Apr 9, 1996
- NEC USA, Inc.
- Srimat T. Chakradhar
- G01 - MEASURING TESTING
Information Patent Grant
Self-testable digital integrator
- Patent number 5,313,469
- Issue date May 17, 1994
- Northern Telecom Limited
- Saman Adham
- G01 - MEASURING TESTING
Information Patent Grant
Device and method for the generation of test vectors and testing me...
- Patent number 5,010,552
- Issue date Apr 23, 1991
- Thomson-CSF
- Bernard Dias
- G01 - MEASURING TESTING
Information Patent Grant
Method of generating tests for a combinational logic circuit
- Patent number 4,996,689
- Issue date Feb 26, 1991
- VLSI Technology, Inc.
- Muhammad A. Samad
- G01 - MEASURING TESTING
Information Patent Grant
Test device for a combinatorial logic circuit and integrated circui...
- Patent number 4,789,821
- Issue date Dec 6, 1988
- U.S. Philips Corporation
- Daniel Baschiera
- G01 - MEASURING TESTING
Information Patent Grant
Method of using complementary logic gates to test for faults in ele...
- Patent number 4,674,090
- Issue date Jun 16, 1987
- Signetics Corporation
- Kong-Chen Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Built in self test input generator for programmable logic arrays
- Patent number 4,672,610
- Issue date Jun 9, 1987
- Motorola, Inc.
- John E. Salick
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Scan Tree Construction
- Publication number 20240151771
- Publication date May 9, 2024
- TSINGHUA UNIVERSITY
- Can Xiang
- G01 - MEASURING TESTING
Information Patent Application
Integrating Machine Learning Delay Estimation in FPGA-Based Emulati...
- Publication number 20240094290
- Publication date Mar 21, 2024
- Synopsys, Inc.
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING DELAY ESTIMATION FOR EMULATION SYSTEMS
- Publication number 20220187367
- Publication date Jun 16, 2022
- Synopsys, Inc.
- Yanhua Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT
- Publication number 20210239759
- Publication date Aug 5, 2021
- KIOXIA Corporation
- Masaki OOISO
- G01 - MEASURING TESTING
Information Patent Application
TESTING DEVICE AND TESTING METHOD FOR TESTING A DEVICE UNDER TEST
- Publication number 20200217891
- Publication date Jul 9, 2020
- ROHDE & SCHWARZ GMBH & CO. KG
- Stefan SCHMIDT
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TEST RESPONSE COMPACTION SCHEME
- Publication number 20190041453
- Publication date Feb 7, 2019
- GLOBALFOUNDRIES INC.
- JAIDEV UDYAVAR SHENOY
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD FOR IMPROVED TEST CONTROLLABILITY AND OBSERVAB...
- Publication number 20090271671
- Publication date Oct 29, 2009
- International Business Machines Corporation
- Mary P. Kusko
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTIO...
- Publication number 20090106614
- Publication date Apr 23, 2009
- Rao H. Desineni
- G01 - MEASURING TESTING
Information Patent Application
Apparatus and method for bit pattern learning and computer product
- Publication number 20060156103
- Publication date Jul 13, 2006
- FUJITSU LIMITED
- Daisuke Maruyama
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for accelerated post-silicon testing and rando...
- Publication number 20040210431
- Publication date Oct 21, 2004
- Keith H. Bierman
- G01 - MEASURING TESTING
Information Patent Application
Method of generating test pattern for integrated circuit
- Publication number 20040153930
- Publication date Aug 5, 2004
- HISASHI YAMAUCHI
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for testing a logic cell in a semiconductor de...
- Publication number 20030229837
- Publication date Dec 11, 2003
- William D. Cox
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Cell architecture to reduce customization in a semiconductor device
- Publication number 20020186045
- Publication date Dec 12, 2002
- William D. Cox
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF GENERATING TEST PATTERN FOR INTEGRATED CIRCUIT
- Publication number 20020046376
- Publication date Apr 18, 2002
- HISASHI YAMAUCHI
- G01 - MEASURING TESTING

for combinational circuits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Integrating machine learning delay estimation in FPGA-based emulati...

Scan tree construction

Machine learning delay estimation for emulation systems

Semiconductor integrated circuit having scan chains sequentially su...

Testing device and testing method for testing a device under test

Test response compaction scheme

Method of fault tolerance in combinational circuits

Apparatus and method for improved test controllability and observab...

System and method for signature-based systematic condition detectio...

Apparatus and method for bit pattern learning and computer product

Method and apparatus for accelerated post-silicon testing and rando...

Method of generating test pattern for integrated circuit

Method for monitoring and improving integrated circuit fabrication...

Circuits and methods for characterizing the speed performance of mu...

Cell architecture to reduce customization in a semiconductor device

Fault propagation path estimating method, fault propagation path es...

Device and method for testing a semiconductor

Method of generating test patterns for a logic circuit, a system pe...

Liquid crystal display driving device and liquid crystal inspection...

Output pin for selectively outputting one of a plurality of signals...

Built-in self tests for large multiplier, adder, or subtractor

Testing VLSI circuits for defects

Self-testable digital integrator

Device and method for the generation of test vectors and testing me...

Method of generating tests for a combinational logic circuit

Test device for a combinatorial logic circuit and integrated circui...

Method of using complementary logic gates to test for faults in ele...

Built in self test input generator for programmable logic arrays

Patents Applicationslast 30 patents

Scan Tree Construction

Integrating Machine Learning Delay Estimation in FPGA-Based Emulati...

MACHINE LEARNING DELAY ESTIMATION FOR EMULATION SYSTEMS

SEMICONDUCTOR INTEGRATED CIRCUIT

TESTING DEVICE AND TESTING METHOD FOR TESTING A DEVICE UNDER TEST

TEST RESPONSE COMPACTION SCHEME

APPARATUS AND METHOD FOR IMPROVED TEST CONTROLLABILITY AND OBSERVAB...

SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTIO...

Apparatus and method for bit pattern learning and computer product

Method and apparatus for accelerated post-silicon testing and rando...

Method of generating test pattern for integrated circuit

Method and apparatus for testing a logic cell in a semiconductor de...

Cell architecture to reduce customization in a semiconductor device

METHOD OF GENERATING TEST PATTERN FOR INTEGRATED CIRCUIT