for dual damascene structures

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CPC
H01L2221/1015

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00

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H01L2221/1015for dual damascene structures

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Patents Grantslast 30 patents

Information Patent Grant
Semiconductor package and method of fabricating semiconductor package
- Patent number 12,125,741
- Issue date Oct 22, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Zi-Jheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and method of fabricating semiconductor package
- Patent number 11,862,512
- Issue date Jan 2, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Zi-Jheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Creating an aligned via and metal line in an integrated circuit inc...
- Patent number 11,081,387
- Issue date Aug 3, 2021
- Marvell Asia Pte, Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming interconnect structure
- Patent number 11,011,419
- Issue date May 18, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Bor-Zen Tien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and method of fabricating semiconductor package
- Patent number 10,937,688
- Issue date Mar 2, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Zi-Jheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of metal wraparound for low via resistance
- Patent number 10,636,737
- Issue date Apr 28, 2020
- QUALCOMM Incorporated
- Junjing Bao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming interconnect structure
- Patent number 10,629,481
- Issue date Apr 21, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Bor-Zen Tien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of creating aligned vias in ultra-high density integrated ci...
- Patent number 10,522,394
- Issue date Dec 31, 2019
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and method of fabricating semiconductor package
- Patent number 10,276,428
- Issue date Apr 30, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd
- Zi-Jheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming interconnect structure
- Patent number 9,716,034
- Issue date Jul 25, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Bor-Zen Tien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma etching method and semiconductor device manufacturing method
- Patent number 9,330,930
- Issue date May 3, 2016
- Tokyo Electron Limited
- Kazuhiro Kubota
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming interconnect structure
- Patent number 9,190,319
- Issue date Nov 17, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsuan-Han Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma etching method and semiconductor device manufacturing method
- Patent number 9,048,178
- Issue date Jun 2, 2015
- Tokyo Electron Limited
- Kazuhiro Kubota
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
- Publication number 20240071814
- Publication date Feb 29, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Zi-Jheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
- Publication number 20230377951
- Publication date Nov 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Zi-Jheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
- Publication number 20210183694
- Publication date Jun 17, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Zi-Jheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming Interconnect Structure
- Publication number 20200227316
- Publication date Jul 16, 2020
- Taiwan Semiconductor Manufacturing Company Ltd.
- Bor-Zen Tien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CREATING AN ALIGNED VIA AND METAL LINE IN AN INTEGRATED CIRCUIT INC...
- Publication number 20200118868
- Publication date Apr 16, 2020
- Marvell World Trade Ltd.
- Runzi CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
- Publication number 20190067086
- Publication date Feb 28, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Zi-Jheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming Interconnect Structure
- Publication number 20170323827
- Publication date Nov 9, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Bor-Zen Tien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method For Forming Interconnect Structure
- Publication number 20140252621
- Publication date Sep 11, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsuan-Han Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLASMA ETCHING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
- Publication number 20140234992
- Publication date Aug 21, 2014
- TOKYO ELECTRON LIMITED
- Kazuhiro Kubota
- H01 - BASIC ELECTRIC ELEMENTS

for dual damascene structures

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor package and method of fabricating semiconductor package

Semiconductor package and method of fabricating semiconductor package

Creating an aligned via and metal line in an integrated circuit inc...

Method for forming interconnect structure

Semiconductor package and method of fabricating semiconductor package

Structure and method of metal wraparound for low via resistance

Method for forming interconnect structure

Method of creating aligned vias in ultra-high density integrated ci...

Semiconductor package and method of fabricating semiconductor package

Method for forming interconnect structure

Plasma etching method and semiconductor device manufacturing method

Method for forming interconnect structure

Plasma etching method and semiconductor device manufacturing method

Patents Applicationslast 30 patents

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

Method for Forming Interconnect Structure

CREATING AN ALIGNED VIA AND METAL LINE IN AN INTEGRATED CIRCUIT INC...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

Method for Forming Interconnect Structure

Method For Forming Interconnect Structure

PLASMA ETCHING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD