Germanium or silicon or Ge-Si on III-V

Industry

CPC
Y10S438/933

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Parent Industries

YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10USPC classification Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10S438/00Semiconductor device manufacturing: process

Current Industry

Y10S438/933Germanium or silicon or Ge-Si on III-V

Industries

Patents Grantslast 30 patents

Information Patent Grant
Silicon germanium source/drain regions
- Patent number 9,887,290
- Issue date Feb 6, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ji-Yin Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving transistor performance through reducing the sa...
- Patent number 9,876,113
- Issue date Jan 23, 2018
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving transistor performance through reducing the sa...
- Patent number 9,680,016
- Issue date Jun 13, 2017
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving transistor performance through reducing the sa...
- Patent number 9,437,710
- Issue date Sep 6, 2016
- Intel Corporation
- Anand Murthy
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for improving transistor performance through reducing the sa...
- Patent number 9,202,889
- Issue date Dec 1, 2015
- Intel Corporation
- Anand Murthy
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
In-situ doping of arsenic for source and drain epitaxy
- Patent number 8,962,400
- Issue date Feb 24, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ji-Yin Tsai
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method of manufacturing semiconductor lasers
- Patent number 8,936,951
- Issue date Jan 20, 2015
- Electronics and Telecommunications Research Institute
- In Gyoo Kim
- G02 - OPTICS
Information Patent Grant
Semiconductor memory cell, device, and method for manufacturing the...
- Patent number 8,927,963
- Issue date Jan 6, 2015
- Institute of Microelectronics, Chinese Academy of Sciences
- Zongliang Huo
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Reduced resistance SiGe FinFET devices and method of forming same
- Patent number 8,895,395
- Issue date Nov 25, 2014
- International Business Machines Corporation
- Pranita Kerber
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Strained silicon nFET and silicon germanium pFET on same wafer
- Patent number 8,883,578
- Issue date Nov 11, 2014
- International Business Machines Corporation
- Veeraraghavan S. Basker
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method of manufacturing semiconductor device
- Patent number 8,871,615
- Issue date Oct 28, 2014
- Kabushiki Kaisha Toshiba
- Shinji Mori
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Strained silicon nFET and silicon germanium pFET on same wafer
- Patent number 8,841,178
- Issue date Sep 23, 2014
- International Business Machines Corporation
- Veeraraghavan S. Basker
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Silicon/germanium particle inks, doped particles, printing and proc...
- Patent number 8,632,702
- Issue date Jan 21, 2014
- NanoGram Corporation
- Henry Hieslmair
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for improving transistor performance through reducing the sa...
- Patent number 8,482,043
- Issue date Jul 9, 2013
- Intel Corporation
- Anand Murthy
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Silicon/germanium oxide particle inks and processes for forming sol...
- Patent number 8,399,878
- Issue date Mar 19, 2013
- NanoGram Corporation
- Henry Hieslmair
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Process for deposition of semiconductor films
- Patent number 8,360,001
- Issue date Jan 29, 2013
- ASM America, Inc.
- Michael A. Todd
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Damascene process for use in fabricating semiconductor structures h...
- Patent number 8,329,559
- Issue date Dec 11, 2012
- The Regents of the University of California
- Hideki Takeuchi
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Silicon/germanium oxide particle inks and processes for forming sol...
- Patent number 8,263,423
- Issue date Sep 11, 2012
- NanoGram Corporation
- Henry Hieslmair
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for manufacturing an III-V engineered substrate and the III-...
- Patent number 8,232,581
- Issue date Jul 31, 2012
- IMEC
- Geoffrey Pourtois
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Semiconductor device manufacturing method
- Patent number 8,232,191
- Issue date Jul 31, 2012
- Fujitsu Semiconductor Limited
- Masahiro Fukuda
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Field-effect transistor and method for fabricating the same
- Patent number 8,187,957
- Issue date May 29, 2012
- Fujitsu Semiconductor Limited
- Keiji Ikeda
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Monolithically integrated silicon and III-V electronics
- Patent number 8,120,060
- Issue date Feb 21, 2012
- Massachusetts Institute of Technology
- Eugene A. Fitzgerald
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for producing a wafer comprising a silicon single crystal su...
- Patent number 8,093,143
- Issue date Jan 10, 2012
- Siltronic AG
- Peter Storck
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Process for deposition of semiconductor films
- Patent number 8,067,297
- Issue date Nov 29, 2011
- ASM America, Inc.
- Michael A. Todd
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Methods for making and using halosilylgermanes
- Patent number 8,043,980
- Issue date Oct 25, 2011
- Arizona Board of Regents, A Body Corporate Acting for and on Behalf of Arizon...
- John Kouvetakis
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Deformation moderation method
- Patent number 8,034,208
- Issue date Oct 11, 2011
- Commissariat a l'Energie Atomique
- Hubert Moriceau
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Monolithically integrated semiconductor materials and devices
- Patent number 8,012,592
- Issue date Sep 6, 2011
- Massachuesetts Institute of Technology
- Eugene A. Fitzgerald
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Silicon/germanium oxide particle inks, inkjet printing and processe...
- Patent number 7,993,947
- Issue date Aug 9, 2011
- NanoGram Corporation
- Henry Hieslmair
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Reconditioned substrates for fabricating compound material wafers
- Patent number 7,968,909
- Issue date Jun 28, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Frederic Dupont
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Non-planar pMOS structure with a strained channel region and an int...
- Patent number 7,960,794
- Issue date Jun 14, 2011
- Intel Corporation
- Brian S Doyle
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
- Publication number 20140287569
- Publication date Sep 25, 2014
- Kabushiki Kaisha Toshiba
- Shinji MORI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER
- Publication number 20140264601
- Publication date Sep 18, 2014
- International Business Machines Corporation
- Veeraraghavan S. BASKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER
- Publication number 20140264755
- Publication date Sep 18, 2014
- International Business Machines Corporation
- Veeraraghavan S. BASKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON/GERMANIUM PARTICLE INKS, DOPED PARTICLES, PRINTING AND PROC...
- Publication number 20140138135
- Publication date May 22, 2014
- NanoGram Corporation
- Henry Hieslmair
- B82 - NANO-TECHNOLOGY
Information Patent Application
SEMICONDUCTOR LASER AND METHOD OF MANUFACTURING THE SAME
- Publication number 20140105235
- Publication date Apr 17, 2014
- ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- In Gyoo KIM
- G02 - OPTICS
Information Patent Application
METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SA...
- Publication number 20130302961
- Publication date Nov 14, 2013
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
In-Situ Doping of Arsenic for Source and Drain Epitaxy
- Publication number 20130011983
- Publication date Jan 10, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ji-Yin Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON/GERMANIUM OXIDE PARTICLE INKS AND PROCESSES FOR FORMING SOL...
- Publication number 20120318168
- Publication date Dec 20, 2012
- NanoGram Corporation
- Henry Hieslmair
- B82 - NANO-TECHNOLOGY
Information Patent Application
SEMICONDUCTOR MEMORY CELL, DEVICE, AND METHOD FOR MANUFACTURING THE...
- Publication number 20120248503
- Publication date Oct 4, 2012
- Zongliang Huo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DAMASCENE PROCESS FOR USE IN FABRICATING SEMICONDUCTOR STRUCTURES H...
- Publication number 20120171798
- Publication date Jul 5, 2012
- The Regents of the University of California
- Hideki Takeuchi
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
SILICON/GERMANIUM OXIDE PARTICLE INKS AND PROCESSES FOR FORMING SOL...
- Publication number 20110281390
- Publication date Nov 17, 2011
- NanoGram Corporation
- Henry Hieslmair
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
SILICON/GERMANIUM OXIDE PARTICLE INKS, INKJET PRINTING AND PROCESSE...
- Publication number 20110109688
- Publication date May 12, 2011
- NanoGram Corporation
- Henry Hieslmair
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Method for improving transistor performance through reducing the sa...
- Publication number 20110101418
- Publication date May 5, 2011
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING COMPOUND MATERIAL WAFERS
- Publication number 20110049528
- Publication date Mar 3, 2011
- S.O.I.Tec Silicon on Insulator Technologies
- Frederic Dupont
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Field-effect transistor and method for fabricating the same
- Publication number 20110045663
- Publication date Feb 24, 2011
- FUJITSU SEMICONDUCTOR
- Keiji IKEDA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
- Publication number 20110014765
- Publication date Jan 20, 2011
- FUJITSU SEMICONDUCTOR LIMITED
- Masahiro Fukuda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for improving transistor performance through reducing the sa...
- Publication number 20110006344
- Publication date Jan 13, 2011
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Manufacturing an III-V Engineered Substrate and the III-...
- Publication number 20100327316
- Publication date Dec 30, 2010
- IMEC
- Geoffrey Pourtois
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method For Producing A Wafer Comprising A Silicon Single Crystal Su...
- Publication number 20100291761
- Publication date Nov 18, 2010
- Siltronic AG
- Peter Storck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH SPEED LATERAL HETEROJUNCTION MISFETS REALIZED BY 2-DIMENSIONAL...
- Publication number 20100159658
- Publication date Jun 24, 2010
- International Business Machines Corporation
- Qiqing Christine Ouyang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Novel Methods for Making and Using Halosilylgermanes
- Publication number 20100151666
- Publication date Jun 17, 2010
- Arizona Board of Regents, a body corporate acting for and on behalf of Arizon...
- John Kouvetakis
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Process for Deposition of Semiconductor Films
- Publication number 20100012030
- Publication date Jan 21, 2010
- ASM AMERICA, INC
- Michael A. Todd
- C30 - CRYSTAL GROWTH
Information Patent Application
MULTILAYER STRUCTURE AND FABRICATION THEREOF
- Publication number 20100006857
- Publication date Jan 14, 2010
- S. O. I. Tec Silicon on Insulator Technologies
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MONOLITHICALLY INTEGRATED PHOTODETECTORS
- Publication number 20090242935
- Publication date Oct 1, 2009
- Massachusetts Institute of Technology
- Eugene A. Fitzgerald
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICI...
- Publication number 20090206413
- Publication date Aug 20, 2009
- International Business Machines Corporation
- Cyril Cabral, JR.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING COMPOUND MATERIAL WAFERS
- Publication number 20090191719
- Publication date Jul 30, 2009
- S.O.I.Tec Silicon on Insulator Technologies
- Frederic Dupont
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEFORMATION MODERATION METHOD
- Publication number 20090133819
- Publication date May 28, 2009
- Hubert Moriceau
- C30 - CRYSTAL GROWTH
Information Patent Application
Method of forming nanowire and method of manufacturing semiconducto...
- Publication number 20090081854
- Publication date Mar 26, 2009
- SAMSUNG ELECTRONICS CO., LTD.
- Jun-youn Kim
- B82 - NANO-TECHNOLOGY
Information Patent Application
PROCESS FOR DEPOSITING LAYERS CONTAINING SILICON AND GERMANIUM
- Publication number 20090081853
- Publication date Mar 26, 2009
- Marcus Schumacher
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
DEFECT REDUCTION BY OXIDATION OF SILICON
- Publication number 20080246019
- Publication date Oct 9, 2008
- International Business Machines Corporation
- Stephen W. Bedell
- H01 - BASIC ELECTRIC ELEMENTS

Germanium or silicon or Ge-Si on III-V

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Silicon germanium source/drain regions

Method for improving transistor performance through reducing the sa...

Method for improving transistor performance through reducing the sa...

Method for improving transistor performance through reducing the sa...

Method for improving transistor performance through reducing the sa...

In-situ doping of arsenic for source and drain epitaxy

Method of manufacturing semiconductor lasers

Semiconductor memory cell, device, and method for manufacturing the...

Reduced resistance SiGe FinFET devices and method of forming same

Strained silicon nFET and silicon germanium pFET on same wafer

Method of manufacturing semiconductor device

Strained silicon nFET and silicon germanium pFET on same wafer

Silicon/germanium particle inks, doped particles, printing and proc...

Method for improving transistor performance through reducing the sa...

Silicon/germanium oxide particle inks and processes for forming sol...

Process for deposition of semiconductor films

Damascene process for use in fabricating semiconductor structures h...

Silicon/germanium oxide particle inks and processes for forming sol...

Method for manufacturing an III-V engineered substrate and the III-...

Semiconductor device manufacturing method

Field-effect transistor and method for fabricating the same

Monolithically integrated silicon and III-V electronics

Method for producing a wafer comprising a silicon single crystal su...

Process for deposition of semiconductor films

Methods for making and using halosilylgermanes

Deformation moderation method

Monolithically integrated semiconductor materials and devices

Silicon/germanium oxide particle inks, inkjet printing and processe...

Reconditioned substrates for fabricating compound material wafers

Non-planar pMOS structure with a strained channel region and an int...

Patents Applicationslast 30 patents

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER

STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER

SILICON/GERMANIUM PARTICLE INKS, DOPED PARTICLES, PRINTING AND PROC...

SEMICONDUCTOR LASER AND METHOD OF MANUFACTURING THE SAME

METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SA...

In-Situ Doping of Arsenic for Source and Drain Epitaxy

SILICON/GERMANIUM OXIDE PARTICLE INKS AND PROCESSES FOR FORMING SOL...

SEMICONDUCTOR MEMORY CELL, DEVICE, AND METHOD FOR MANUFACTURING THE...

DAMASCENE PROCESS FOR USE IN FABRICATING SEMICONDUCTOR STRUCTURES H...

SILICON/GERMANIUM OXIDE PARTICLE INKS AND PROCESSES FOR FORMING SOL...

SILICON/GERMANIUM OXIDE PARTICLE INKS, INKJET PRINTING AND PROCESSE...

Method for improving transistor performance through reducing the sa...

METHODS FOR FABRICATING COMPOUND MATERIAL WAFERS

Field-effect transistor and method for fabricating the same

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Method for improving transistor performance through reducing the sa...

Method for Manufacturing an III-V Engineered Substrate and the III-...

Method For Producing A Wafer Comprising A Silicon Single Crystal Su...

HIGH SPEED LATERAL HETEROJUNCTION MISFETS REALIZED BY 2-DIMENSIONAL...

Novel Methods for Making and Using Halosilylgermanes

Process for Deposition of Semiconductor Films

MULTILAYER STRUCTURE AND FABRICATION THEREOF

MONOLITHICALLY INTEGRATED PHOTODETECTORS

CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICI...

METHODS FOR FABRICATING COMPOUND MATERIAL WAFERS

DEFORMATION MODERATION METHOD

Method of forming nanowire and method of manufacturing semiconducto...

PROCESS FOR DEPOSITING LAYERS CONTAINING SILICON AND GERMANIUM

DEFECT REDUCTION BY OXIDATION OF SILICON