Hardware for routing the test signal within the device under test to the circuits to be tested

Industry

CPC
G01R31/31723

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Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/31723Hardware for routing the test signal within the device under test to the circuits to be tested

Industries

Patents Grantslast 30 patents

Information Patent Grant
Process for scan chain in a memory
- Patent number 11,971,448
- Issue date Apr 30, 2024
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test circuit using clock gating scheme to hold capture procedure an...
- Patent number 11,959,965
- Issue date Apr 16, 2024
- Samsung Electronics Co., Ltd.
- Giha Nam
- G01 - MEASURING TESTING
Information Patent Grant
Built-in self-test for die-to-die physical interfaces
- Patent number 11,940,491
- Issue date Mar 26, 2024
- Apple Inc.
- Fabien S. Faure
- G01 - MEASURING TESTING
Information Patent Grant
Benchmark circuit on a semiconductor wafer and method for operating...
- Patent number 11,927,628
- Issue date Mar 12, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chu-Feng Liao
- G01 - MEASURING TESTING
Information Patent Grant
Generating multiple pseudo static control signals using on-chip JTA...
- Patent number 11,899,063
- Issue date Feb 13, 2024
- Texas Instruments Incorporated
- Mudasir Shafat Kawoosa
- G01 - MEASURING TESTING
Information Patent Grant
Scan testing using scan frames with embedded commands
- Patent number 11,879,941
- Issue date Jan 23, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Time offset method and device for test signal
- Patent number 11,860,226
- Issue date Jan 2, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Liang Chen
- G01 - MEASURING TESTING
Information Patent Grant
Interposer circuit
- Patent number 11,835,581
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 11,835,578
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
AT-speed test access port operations
- Patent number 11,808,810
- Issue date Nov 7, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for reusing manufacturing content across multi...
- Patent number 11,808,811
- Issue date Nov 7, 2023
- Intel Corporation
- Kalyana Kantipudi
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,782,091
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D TAP and scan port architectures
- Patent number 11,762,014
- Issue date Sep 19, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Addressable test access port apparatus
- Patent number 11,747,397
- Issue date Sep 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan test control decoder with storage elements for use within inte...
- Patent number 11,747,399
- Issue date Sep 5, 2023
- Texas Instruments Incorporated
- Mudasir Shafat Kawoosa
- G01 - MEASURING TESTING
Information Patent Grant
Scan testing using scan frames with embedded commands
- Patent number 11,740,286
- Issue date Aug 29, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Device, system and method to support communication of test, debug o...
- Patent number 11,698,412
- Issue date Jul 11, 2023
- Intel Corporation
- Rolf H. Kuehnis
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain for memory with reduced power consumption
- Patent number 11,693,056
- Issue date Jul 4, 2023
- Ceremorphic, Inc.
- Robert F. Wiser
- G01 - MEASURING TESTING
Information Patent Grant
System, apparatus and method for functional testing of one or more...
- Patent number 11,686,767
- Issue date Jun 27, 2023
- Intel Corporation
- Lakshminarayana Pappu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip, chip testing method and electronic device
- Patent number 11,686,771
- Issue date Jun 27, 2023
- CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO., LTD.
- Yuqian Cedric Wong
- G01 - MEASURING TESTING
Information Patent Grant
System and method of testing single DUT through multiple cores in p...
- Patent number 11,686,768
- Issue date Jun 27, 2023
- Test Research, Inc.
- Ching-Chih Lin
- G01 - MEASURING TESTING
Information Patent Grant
Automatic test pattern generation circuitry in multi power domain s...
- Patent number 11,680,982
- Issue date Jun 20, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Falling clock edge JTAG bus routers
- Patent number 11,680,985
- Issue date Jun 20, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Test access port with address and command capability
- Patent number 11,680,981
- Issue date Jun 20, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit having an in-situ circuit for detecting an impen...
- Patent number 11,680,983
- Issue date Jun 20, 2023
- NXP USA, INC.
- Anis Mahmoud Jarrar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
3D stacked die test architecture
- Patent number 11,675,007
- Issue date Jun 13, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Built-in self-test for die-to-die physical interfaces
- Patent number 11,662,380
- Issue date May 30, 2023
- Apple Inc.
- Fabien S. Faure
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus for device access port selection
- Patent number 11,656,278
- Issue date May 23, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TSV testing using test circuits and grounding means
- Patent number 11,644,503
- Issue date May 9, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTERPOSER CIRCUIT
- Publication number 20240094289
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR ACCESS CONTROL OF A PLURALITY OF INSTRUMENTS...
- Publication number 20240061041
- Publication date Feb 22, 2024
- Erik Larsson
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20240061038
- Publication date Feb 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240019489
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
- Publication number 20240012050
- Publication date Jan 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230417831
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20230400513
- Publication date Dec 14, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
- Publication number 20230384376
- Publication date Nov 30, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Built-in Self-Test for Die-to-Die Physical Interfaces
- Publication number 20230384377
- Publication date Nov 30, 2023
- Apple Inc.
- Fabien S. Faure
- G01 - MEASURING TESTING
Information Patent Application
FALLING CLOCK EDGE JTAG BUS ROUTERS
- Publication number 20230333163
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY
- Publication number 20230333159
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
CONFIGURABLE BOUNDARY SCAN
- Publication number 20230314509
- Publication date Oct 5, 2023
- Intel Corporation
- Rohini Krishnan
- G01 - MEASURING TESTING
Information Patent Application
DEVICE ACCESS PORT SELECTION
- Publication number 20230296670
- Publication date Sep 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Process for Scan Chain in a Memory
- Publication number 20230296672
- Publication date Sep 21, 2023
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHOD FOR REUSING MANUFACTURING CONTENT ACROSS MULTI...
- Publication number 20230288479
- Publication date Sep 14, 2023
- Intel Corporation
- Kalyana KANTIPUDI
- G01 - MEASURING TESTING
Information Patent Application
Array of Through-Silicon Via Contact Points on a Semiconductor Die
- Publication number 20230273258
- Publication date Aug 31, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN FRAME BASED TEST ACCESS MECHANISMS
- Publication number 20230258715
- Publication date Aug 17, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTERPOSER CIRCUIT
- Publication number 20230204663
- Publication date Jun 29, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON-CHIP DISTRIBUTION OF TEST DATA FOR MULTIPLE DIES
- Publication number 20230204662
- Publication date Jun 29, 2023
- Advanced Micro Devices Products (China) Co. Ltd.,
- Arie MARGULIS
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain for Memory with Reduced Power Consumption
- Publication number 20230194607
- Publication date Jun 22, 2023
- Ceremorphic, Inc.
- Shakti SINGH
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20230194604
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DEVICE
- Publication number 20230184586
- Publication date Jun 15, 2023
- InnoLux Corporation
- Kazuyuki HASHIMOTO
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD OF MONITORING PERFORMANCE OF AN ELECTRONIC DEVICE
- Publication number 20230184830
- Publication date Jun 15, 2023
- Samsung Electronics Co., Ltd.
- Sunwook KIM
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGIS...
- Publication number 20230176123
- Publication date Jun 8, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20230160959
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230160958
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AN...
- Publication number 20230152372
- Publication date May 18, 2023
- Samsung Electronics Co., Ltd.
- GIHA NAM
- G01 - MEASURING TESTING
Information Patent Application
BENCHMARK CIRCUIT ON A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING...
- Publication number 20230014148
- Publication date Jan 19, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- CHU-FENG LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TIME OFFSET METHOD AND DEVICE FOR TEST SIGNAL
- Publication number 20230003796
- Publication date Jan 5, 2023
- CHANGXIN MEMORY TECHNOLOGIES, INC
- Liang CHEN
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS FOR DEVICE ACCESS PORT SELECTION
- Publication number 20220413041
- Publication date Dec 29, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Hardware for routing the test signal within the device under test to the circuits to be tested

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Process for scan chain in a memory

Single “A” latch with an array of “B” latches

Test circuit using clock gating scheme to hold capture procedure an...

Built-in self-test for die-to-die physical interfaces

Benchmark circuit on a semiconductor wafer and method for operating...

Generating multiple pseudo static control signals using on-chip JTA...

Scan testing using scan frames with embedded commands

Time offset method and device for test signal

Interposer circuit

Selectable JTAG or trace access with data store and output

AT-speed test access port operations

Apparatus and method for reusing manufacturing content across multi...

Wafer scale testing using a 2 signal JTAG interface

3D TAP and scan port architectures

Addressable test access port apparatus

Scan test control decoder with storage elements for use within inte...

Scan testing using scan frames with embedded commands

Device, system and method to support communication of test, debug o...

Scan chain for memory with reduced power consumption

System, apparatus and method for functional testing of one or more...

Chip, chip testing method and electronic device

System and method of testing single DUT through multiple cores in p...

Automatic test pattern generation circuitry in multi power domain s...

Falling clock edge JTAG bus routers

Test access port with address and command capability

Integrated circuit having an in-situ circuit for detecting an impen...

3D stacked die test architecture

Built-in self-test for die-to-die physical interfaces

Apparatus for device access port selection

TSV testing using test circuits and grounding means

Patents Applicationslast 30 patents

INTERPOSER CIRCUIT

SYSTEM AND METHOD FOR ACCESS CONTROL OF A PLURALITY OF INSTRUMENTS...

AT-SPEED TEST ACCESS PORT OPERATIONS

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

3D TAP & SCAN PORT ARCHITECTURES

ADDRESSABLE TEST ACCESS PORT

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

Built-in Self-Test for Die-to-Die Physical Interfaces

FALLING CLOCK EDGE JTAG BUS ROUTERS

TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY

CONFIGURABLE BOUNDARY SCAN

DEVICE ACCESS PORT SELECTION

Process for Scan Chain in a Memory

APPARATUS AND METHOD FOR REUSING MANUFACTURING CONTENT ACROSS MULTI...

Array of Through-Silicon Via Contact Points on a Semiconductor Die

SCAN FRAME BASED TEST ACCESS MECHANISMS

INTERPOSER CIRCUIT

ON-CHIP DISTRIBUTION OF TEST DATA FOR MULTIPLE DIES

Scan Chain for Memory with Reduced Power Consumption

AT-SPEED TEST ACCESS PORT OPERATIONS

ELECTRONIC DEVICE

SYSTEM AND METHOD OF MONITORING PERFORMANCE OF AN ELECTRONIC DEVICE

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGIS...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

3D TAP & SCAN PORT ARCHITECTURES

TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AN...

BENCHMARK CIRCUIT ON A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING...

TIME OFFSET METHOD AND DEVICE FOR TEST SIGNAL

APPARATUS FOR DEVICE ACCESS PORT SELECTION