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CPC
Y10S148/08

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YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10USPC classification Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10S148/00Metal treatment

Current Industry

Y10S148/08Infra-red

Industries

Patents Grantslast 30 patents

Information Patent Grant
Method of manufacturing a 1-inch diameter glass substrate for a mag...
- Patent number 6,314,764
- Issue date Nov 13, 2001
- Saatec Engineering Corporation
- Yasuaki Sakamoto
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of manufacturing a 2-5 inch diameter glass substrate for a m...
- Patent number 6,314,763
- Issue date Nov 13, 2001
- Saatec Engineering Corporation
- Yasuaki Sakamoto
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Insulating material, substrate covered with an insulating film, met...
- Patent number 6,307,225
- Issue date Oct 23, 2001
- Sharp Kabushiki Kaisha
- Takeshi Kijima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a porous insulation film
- Patent number 6,218,318
- Issue date Apr 17, 2001
- Fujitsu Limited
- Yoshiyuki Ohkura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical transistor having top and bottom surface isolation
- Patent number 6,194,773
- Issue date Feb 27, 2001
- Texas Instruments Incorporated
- Satwinder Malhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface reforming method of a metal product
- Patent number 6,136,385
- Issue date Oct 24, 2000
- Saatec Engineering Corporation
- Yasuaki Sakamoto
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of fabricating integrated circuits with oxidized isolation
- Patent number 6,093,620
- Issue date Jul 25, 2000
- National Semiconductor Corporation
- Douglas L. Peltzer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Damascene isolation of CMOS transistors
- Patent number 5,981,326
- Issue date Nov 9, 1999
- Frank M. Wanlass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for characterizing and controlling the heat tr...
- Patent number 5,981,919
- Issue date Nov 9, 1999
- Bouillon, Inc.
- James W. Masten
- C21 - METALLURGY OF IRON
Information Patent Grant
Fabrication of semiconductor structure having two levels of buried...
- Patent number 5,899,714
- Issue date May 4, 1999
- National Semiconductor Corporation
- Douglas R. Farrenkopf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having two levels of buried regions
- Patent number 5,889,315
- Issue date Mar 30, 1999
- National Semiconductor Corporation
- Douglas R. Farrenkopf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method for manufacturing the same
- Patent number 5,880,487
- Issue date Mar 9, 1999
- Kabushiki Kaisha Toshiba
- Chisato Furukawa
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Semiconductor device with selectively patterned connection pad laye...
- Patent number 5,818,091
- Issue date Oct 6, 1998
- Samsung Electronics Co., Ltd.
- Yong-hee Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Zener diodes on the same wafer with BiCDMOS structures
- Patent number 5,751,054
- Issue date May 12, 1998
- Siliconix Incorporated
- Hamza Yilmaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a semiconductor device
- Patent number 5,683,937
- Issue date Nov 4, 1997
- Kabushiki Kaisha Toshiba
- Chisato Furukawa
- B82 - NANO-TECHNOLOGY
Information Patent Grant
MOS transistor having adjusted threshold voltage formed along with...
- Patent number 5,618,743
- Issue date Apr 8, 1997
- Siliconix Incorporated
- Richard K. Williams
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PMOS transistors with different breakdown voltages formed in the sa...
- Patent number 5,583,061
- Issue date Dec 10, 1996
- Siliconix Incorporated
- Richard K. Williams
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
BiCDMOS process technology
- Patent number 5,559,044
- Issue date Sep 24, 1996
- Siliconix Incorporated
- Richard K. Williams
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a zener diode region and an isolation region
- Patent number 5,547,880
- Issue date Aug 20, 1996
- Siliconix Incorporated
- Richard K. Williams
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a bipolar transistor having selected breakdown v...
- Patent number 5,541,123
- Issue date Jul 30, 1996
- Siliconix Incorporated
- Richard K. Williams
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a lateral MOS transistor having lightly doped dr...
- Patent number 5,541,125
- Issue date Jul 30, 1996
- Siliconix Incorporated
- Richard K. Williams
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing dielectrics dividing wafer with isolated r...
- Patent number 5,496,760
- Issue date Mar 5, 1996
- Fuji Electric Company, Ltd.
- Kazuo Matsuzaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a CMOS semiconductor device
- Patent number 5,484,739
- Issue date Jan 16, 1996
- Samsung Electronics Co., Ltd.
- Yong-hee Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolated DMOS IC technology
- Patent number 5,485,027
- Issue date Jan 16, 1996
- Siliconix Incorporated
- Richard K. Williams
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shield assembly for semiconductor wafer supports
- Patent number 5,476,520
- Issue date Dec 19, 1995
- Applied Materials, Inc.
- Peter R. Jaffe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a real time ion implantation metal silicide monitor
- Patent number 5,451,529
- Issue date Sep 19, 1995
- Taiwan Semiconductor Manufacturing Company
- Shun-Liang Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a CMOS device with reduced number of photoli...
- Patent number 5,439,834
- Issue date Aug 8, 1995
- Winbond Electronics Corp.
- Heng-Tien Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep collection guard ring
- Patent number 5,438,005
- Issue date Aug 1, 1995
- Winbond Electronics Corp.
- Wen-Yueh Jang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming twin well CMOS integrated circuits
- Patent number 5,429,958
- Issue date Jul 4, 1995
- Harris Corporation
- Dyer A. Matlock
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
BICDMOS structures
- Patent number 5,426,328
- Issue date Jun 20, 1995
- Siliconix Incorporated
- Hamza Yilmaz
- H01 - BASIC ELECTRIC ELEMENTS

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method of manufacturing a 1-inch diameter glass substrate for a mag...

Method of manufacturing a 2-5 inch diameter glass substrate for a m...

Insulating material, substrate covered with an insulating film, met...

Semiconductor device having a porous insulation film

Vertical transistor having top and bottom surface isolation

Surface reforming method of a metal product

Method of fabricating integrated circuits with oxidized isolation

Damascene isolation of CMOS transistors

Method and apparatus for characterizing and controlling the heat tr...

Fabrication of semiconductor structure having two levels of buried...

Semiconductor structure having two levels of buried regions

Semiconductor device and method for manufacturing the same

Semiconductor device with selectively patterned connection pad laye...

Zener diodes on the same wafer with BiCDMOS structures

Method of making a semiconductor device

MOS transistor having adjusted threshold voltage formed along with...

PMOS transistors with different breakdown voltages formed in the sa...

BiCDMOS process technology

Method for forming a zener diode region and an isolation region

Method for forming a bipolar transistor having selected breakdown v...

Method for forming a lateral MOS transistor having lightly doped dr...

Method for manufacturing dielectrics dividing wafer with isolated r...

Method for manufacturing a CMOS semiconductor device

Isolated DMOS IC technology

Shield assembly for semiconductor wafer supports

Method of making a real time ion implantation metal silicide monitor

Method for fabricating a CMOS device with reduced number of photoli...

Deep collection guard ring

Process for forming twin well CMOS integrated circuits

BICDMOS structures