Lateral isolation by refilling of trenches with dielectric material

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CPC
H01L21/76283

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Current Industry

H01L21/76283Lateral isolation by refilling of trenches with dielectric material

Industries

Patents Grantslast 30 patents

Information Patent Grant
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- Taiwan Semiconductor Manufacturing Company, Ltd
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Information Patent Grant
Method for preparing semiconductor device structure with multiple l...
- Patent number 11,764,105
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- NANYA TECHNOLOGY CORPORATION
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Bulk substrates with a self-aligned buried polycrystalline layer
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Information Patent Grant
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- Taiwan Semiconductor Manufacturing Co., Ltd.
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Information Patent Grant
Multilayer isolation structure for high voltage silicon-on-insulato...
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- Issue date Apr 25, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
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Lateral isolation by refilling of trenches with dielectric material

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Composite structure, intended for a planar co-integration of electr...

High voltage device with boosted breakdown voltage

Structures for radiofrequency applications and related methods

Back side processing of integrated circuit structures to form insul...

Dielectric-filled trench isolation of vias

Integrated circuit device

Method for preparing semiconductor device structure with multiple l...

Method of forming a deep trench isolation structure for isolation o...

Multiple thickness semiconductor-on-insulator field effect transist...

Semiconductor device with sidewall interconnection structure, metho...

Semiconductor isolation structure and method of making the same

Nanosheet IC device with single diffusion break

Trench shield isolation layer

3D semiconductor device and structure

Relating to SOI wafers and devices with buried stressors

Isolation gap filling process for embedded dram using spacer material

Integrated circuit with active region jogs

Semiconductor feature and method for manufacturing the same

Method for preparing semiconductor device structure with multiple l...

Bulk substrates with a self-aligned buried polycrystalline layer

Transistor with embedded isolation layer in bulk substrate

Semiconductor device with sidewall interconnection structure, metho...

Integrated circuit structure and method with hybrid orientation for...

Wet clean process for fabricating semiconductor devices

Transistor level interconnection methodologies utilizing 3D interco...

Structures and methods for reducing process charging damages

Multilayer isolation structure for high voltage silicon-on-insulato...

Method for forming transistor structures

Embedded memory using SOI structures and methods

FinFET isolation structure

Patents Applicationslast 30 patents

METAL OXIDE SEMICONDUCTOR DEVICES AND INTEGRATION METHODS

DIRECT BACKSIDE SELF-ALIGNED CONTACT

DEVICE WITH LATERALLY GRADED CHANNEL REGION

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor Structures And Methods Of Forming The Same

GAA DEVICE WITH THE SUBSTRATE INCLUDING EMBEDDED INSULATING STRUCTU...

EMBEDDED SOI STRUCTURE FOR LOW LEAKAGE MOS CAPACITOR

INTEGRATED CIRCUIT DEVICE

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SOI WAFERS AND DEVICES WITH BURIED STRESSORS

Integrated Circuit Structure and Method with Hybrid Orientation for...

INTEGRATED CIRCUIT WITH ACTIVE REGION JOGS

LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE

SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF

SEMICONDUCTOR FEATURE AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR FABRICATION PROCESS

Trench Isolation Connectors for Stacked Structures

PROFILE OF DEEP TRENCH ISOLATION STRUCTURE FOR ISOLATION OF HIGH-VO...

MULTILAYER ISOLATION STRUCTURE FOR HIGH VOLTAGE SILICON-ON-INSULATO...

INTEGRATED CIRCUIT STRUCTURES HAVING CONDUCTIVE STRUCTURES IN FIN I...

METHOD FOR FORMING INTEGRATED CIRCUIT

STRUCTURES AND METHODS FOR REDUCING PROCESS CHARGING DAMAGES

Metal Gate Structure And Methods Of Fabricating Thereof

FINFET ISOLATION STRUCTURE

SEMICONDUCTOR DEVICE WITH TRENCH ISOLATION STRUCTURES IN A TRANSITI...

IC STRUCTURE INCLUDING POROUS SEMICONDUCTOR LAYER IN BULK SUBSTRATE...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

SWITCHES IN BULK SUBSTRATE

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF