not being interposed between the wire connector and the bonding area

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CPC
H01L2224/48496

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/48496not being interposed between the wire connector and the bonding area

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Stacked microfeature devices and associated methods
- Patent number 11,887,970
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Mung Suan Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Straight wirebonding of silicon dies
- Patent number 11,456,272
- Issue date Sep 27, 2022
- Western Digital Technologies, Inc.
- Kirubakaran Periyannan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked microfeature devices and associated methods
- Patent number 11,373,979
- Issue date Jun 28, 2022
- Micron Technology, Inc.
- Mung Suan Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked microfeature devices and associated methods
- Patent number 10,062,667
- Issue date Aug 28, 2018
- Micron Technology, Inc.
- Mung Suan Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for bonding a hermetic module to an electrode array
- Patent number 9,984,994
- Issue date May 29, 2018
- The Charles Stark Draper Laboratory, Inc.
- Tirunelveli Sriram
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Submount, encapsulated semiconductor element, and methods of manufa...
- Patent number 9,263,411
- Issue date Feb 16, 2016
- Advanced Photonics, Inc.
- Xueliang Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication method of multi-chip stack structure
- Patent number 7,981,729
- Issue date Jul 19, 2011
- Siliconware Precision Industries Co., Ltd.
- Jung-Pin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip stack structure and fabrication method thereof
- Patent number 7,768,106
- Issue date Aug 3, 2010
- Siliconware Precision Industries Co., Ltd.
- Jung-Ping Huang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STRAIGHT WIREBONDING OF SILICON DIES
- Publication number 20220084979
- Publication date Mar 17, 2022
- Western Digital Technologies, Inc.
- Kirubakaran Periyannan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS
- Publication number 20180358331
- Publication date Dec 13, 2018
- Micron Technology, Inc.
- Mung Suan Heng
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
METHOD FOR BONDING A HERMETIC MODULE TO AN ELECTRODE ARRAY
- Publication number 20170154867
- Publication date Jun 1, 2017
- The Charles Stark Draper Laboratory, Inc.
- Tirunelveli Sriram
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS
- Publication number 20170084585
- Publication date Mar 23, 2017
- Micron Technology, Inc.
- Mung Suan Heng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE
- Publication number 20100255635
- Publication date Oct 7, 2010
- Siliconware Precision Industries Co., Ltd.
- Jung-Pin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-chip stack structure and fabrication method thereof
- Publication number 20080224289
- Publication date Sep 18, 2008
- Siliconware Precision Industries Co., Ltd.
- Jung-Pin Huang
- H01 - BASIC ELECTRIC ELEMENTS

not being interposed between the wire connector and the bonding area

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Stacked microfeature devices and associated methods

Straight wirebonding of silicon dies

Stacked microfeature devices and associated methods

Stacked microfeature devices and associated methods

Method for bonding a hermetic module to an electrode array

Submount, encapsulated semiconductor element, and methods of manufa...

Fabrication method of multi-chip stack structure

Multi-chip stack structure and fabrication method thereof

Patents Applicationslast 30 patents

STRAIGHT WIREBONDING OF SILICON DIES

STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS

METHOD FOR BONDING A HERMETIC MODULE TO AN ELECTRODE ARRAY

STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS

FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE

Multi-chip stack structure and fabrication method thereof