Reconfiguring for testing

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CPC
G01R31/3185

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/3185Reconfiguring for testing

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Photonic wafer level testing systems, devices, and methods of opera...
- Patent number 12,216,020
- Issue date Feb 4, 2025
- STMicroelectronics S.r.l.
- Marco Piazza
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain analysis using predefined capture signature
- Patent number 12,216,161
- Issue date Feb 4, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Grant
Performing scan data transfer inside multi-die package with serdes...
- Patent number 12,216,162
- Issue date Feb 4, 2025
- Advanced Micro Devices, Inc.
- Ahmet Tokuz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die aging measurements for dynamic timing modeling
- Patent number 12,216,150
- Issue date Feb 4, 2025
- Altera Corporation
- Dheeraj Subbareddy
- G01 - MEASURING TESTING
Information Patent Grant
Device access port selection
- Patent number 12,210,060
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Wafer level methods of testing semiconductor devices using internal...
- Patent number 12,203,980
- Issue date Jan 21, 2025
- Samsung Electronics Co., Ltd.
- Ahn Choi
- G01 - MEASURING TESTING
Information Patent Grant
Test-time optimization with few slow scan pads
- Patent number 12,203,985
- Issue date Jan 21, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain circuit and corresponding method
- Patent number 12,203,984
- Issue date Jan 21, 2025
- STMicroelectronics S.r.l.
- Marco Casarsa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Diagnostic device
- Patent number 12,203,981
- Issue date Jan 21, 2025
- The Boeing Company
- Ian M. Dayton
- G01 - MEASURING TESTING
Information Patent Grant
Test method of storage device implemented in multi-chip package (MC...
- Patent number 12,205,852
- Issue date Jan 21, 2025
- Samsung Electronics Co., Ltd.
- Sangmin An
- G11 - INFORMATION STORAGE
Information Patent Grant
Error protection analysis of an integrated circuit
- Patent number 12,188,979
- Issue date Jan 7, 2025
- International Business Machines Corporation
- Benjamin Neil Trombley
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for post-binding testing of 2.5D chiplet
- Patent number 12,188,984
- Issue date Jan 7, 2025
- Nanjing University Of Posts And Telecommunications
- Zhikuang Cai
- G01 - MEASURING TESTING
Information Patent Grant
Test access port with address and command capability
- Patent number 12,188,980
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit having test circuitry for memory sub-systems
- Patent number 12,181,522
- Issue date Dec 31, 2024
- NXP USA, INC.
- Alexander Hoefler
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed test access port operations
- Patent number 12,181,521
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data correction and phase optimization in high-speed receivers
- Patent number 12,181,523
- Issue date Dec 31, 2024
- Diodes Incorporated
- Yu-Wei Lin
- G01 - MEASURING TESTING
Information Patent Grant
Chip test circuit and circuit test method
- Patent number 12,181,519
- Issue date Dec 31, 2024
- Huawei Technologies Co., Ltd.
- Changming Cui
- G01 - MEASURING TESTING
Information Patent Grant
System testing using partitioned and controlled noise
- Patent number 12,174,251
- Issue date Dec 24, 2024
- International Business Machines Corporation
- Mary P. Kusko
- G01 - MEASURING TESTING
Information Patent Grant
Fault detection method and related apparatus
- Patent number 12,174,254
- Issue date Dec 24, 2024
- Huawei Technologies Co., Ltd.
- Zhe Tao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TSV testing
- Patent number 12,163,998
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bi-directional scan flip-flop circuit and method
- Patent number 12,166,487
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus to inject errors in a memory block and validat...
- Patent number 12,164,401
- Issue date Dec 10, 2024
- NXP B.V.
- Umesh Pratap Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Registers
- Patent number 12,158,499
- Issue date Dec 3, 2024
- Nordic Semiconductor ASA
- Matti Samuli Leinonen
- G01 - MEASURING TESTING
Information Patent Grant
System and method which can reduce circuit area while performing te...
- Patent number 12,158,500
- Issue date Dec 3, 2024
- Realtek Semiconductor Corp.
- Yu-Cheng Lo
- G01 - MEASURING TESTING
Information Patent Grant
Testing circuitry for testing multicycle path circuit
- Patent number 12,158,498
- Issue date Dec 3, 2024
- Realtek Semiconductor Corporation
- Chun-Yi Kuo
- G01 - MEASURING TESTING
Information Patent Grant
Scan testable through silicon VIAs
- Patent number 12,154,835
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic circuit and method of error correction
- Patent number 12,153,088
- Issue date Nov 26, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chia-Chun Liao
- G01 - MEASURING TESTING
Information Patent Grant
Commanded JTAG test access port operations
- Patent number 12,153,090
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
TVF transition coverage with self-test and production-test time red...
- Patent number 12,146,911
- Issue date Nov 19, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION
- Publication number 20250035703
- Publication date Jan 30, 2025
- STMicroelectronics International N.V.
- Ankur BAL
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO...
- Publication number 20250027993
- Publication date Jan 23, 2025
- QUALCOMM Incorporated
- Paul POLICKE
- G01 - MEASURING TESTING
Information Patent Application
MONITOR CIRCUIT TO DETERMINE INTEGRATED CIRCUIT CONDITION BASED ON...
- Publication number 20250027996
- Publication date Jan 23, 2025
- QUALCOMM Incorporated
- Anatoly GELMAN
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING
- Publication number 20250027992
- Publication date Jan 23, 2025
- Samsung Electronics Co., Ltd.
- Seaeun Park
- G01 - MEASURING TESTING
Information Patent Application
TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS
- Publication number 20250027994
- Publication date Jan 23, 2025
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
- Publication number 20250027995
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHOD
- Publication number 20250020718
- Publication date Jan 16, 2025
- Anritsu Corporation
- Hironori YOSHIOKA
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME
- Publication number 20250020719
- Publication date Jan 16, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mohammed Moiz Khan
- G01 - MEASURING TESTING
Information Patent Application
PROTECTION OF THE CONTENT OF A FUSE MEMORY
- Publication number 20250004051
- Publication date Jan 2, 2025
- STMicroelectronics (Grenoble 2) SAS
- Mark Trimmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...
- Publication number 20240426908
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Andrea Floridia
- G01 - MEASURING TESTING
Information Patent Application
TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES
- Publication number 20240426907
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Shiv Kumar Vats
- G01 - MEASURING TESTING
Information Patent Application
LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME
- Publication number 20240426909
- Publication date Dec 26, 2024
- SAMSUNG ELECTRONICS CO,. LTD.
- Sangsoon IM
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING
- Publication number 20240418776
- Publication date Dec 19, 2024
- NORDIC SEMICONDUCTOR ASA
- Ashraf MOHAMMED
- G01 - MEASURING TESTING
Information Patent Application
Diagnostic Device
- Publication number 20240418773
- Publication date Dec 19, 2024
- The Boeing Company
- Ian M. Dayton
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR TRACKING AND MANAGING ACTIVITIES OF TESTBENCH...
- Publication number 20240418775
- Publication date Dec 19, 2024
- HCL America Inc.
- MANICKAM MUTHIAH
- G01 - MEASURING TESTING
Information Patent Application
TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...
- Publication number 20240402249
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240402247
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR PROTECTION ANALYSIS OF AN INTEGRATED CIRCUIT
- Publication number 20240402246
- Publication date Dec 5, 2024
- International Business Machines Corporation
- BENJAMIN NEIL TROMBLEY
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Analysis Using Predefined Capture Signature
- Publication number 20240393394
- Publication date Nov 28, 2024
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSION-BASED SCAN TEST SYSTEM
- Publication number 20240393393
- Publication date Nov 28, 2024
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
D FLIP-FLOP HAVING MULTIPLEXER FUNCTION
- Publication number 20240388281
- Publication date Nov 21, 2024
- SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.
- Zhijun FAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION
- Publication number 20240385241
- Publication date Nov 21, 2024
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION
- Publication number 20240385242
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- CHIA-CHUN LIAO
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20240385244
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...
- Publication number 20240369629
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERIAL TEST CIRCUIT FOR CONTROLLABLE CHIPLETS
- Publication number 20240369631
- Publication date Nov 7, 2024
- Nanjing University Of Posts And Telecommunications
- Zhikuang CAI
- G01 - MEASURING TESTING
Information Patent Application
MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS
- Publication number 20240369632
- Publication date Nov 7, 2024
- Micron Technology, Inc.
- Kenneth M. Curewitz
- G01 - MEASURING TESTING
Information Patent Application
ARRAY OF UNIT CELLS HAVING PAD STRUCTURES
- Publication number 20240369626
- Publication date Nov 7, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Yu-Ching CHIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLITCH FILTER
- Publication number 20240369630
- Publication date Nov 7, 2024
- NORDIC SEMICONDUCTOR ASA
- Christian HERGOT
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
- Publication number 20240361384
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING

Reconfiguring for testing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Photonic wafer level testing systems, devices, and methods of opera...

Scan chain analysis using predefined capture signature

Performing scan data transfer inside multi-die package with serdes...

On-die aging measurements for dynamic timing modeling

Device access port selection

Wafer level methods of testing semiconductor devices using internal...

Test-time optimization with few slow scan pads

Scan chain circuit and corresponding method

Diagnostic device

Test method of storage device implemented in multi-chip package (MC...

Error protection analysis of an integrated circuit

Circuit and method for post-binding testing of 2.5D chiplet

Test access port with address and command capability

Integrated circuit having test circuitry for memory sub-systems

At-speed test access port operations

Data correction and phase optimization in high-speed receivers

Chip test circuit and circuit test method

System testing using partitioned and controlled noise

Fault detection method and related apparatus

3D tap and scan port architectures

TSV testing

Bi-directional scan flip-flop circuit and method

Method and apparatus to inject errors in a memory block and validat...

Registers

System and method which can reduce circuit area while performing te...

Testing circuitry for testing multicycle path circuit

Scan testable through silicon VIAs

Electronic circuit and method of error correction

Commanded JTAG test access port operations

TVF transition coverage with self-test and production-test time red...

Patents Applicationslast 30 patents

SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION

INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO...

MONITOR CIRCUIT TO DETERMINE INTEGRATED CIRCUIT CONDITION BASED ON...

INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING

TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS

ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHOD

SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME

PROTECTION OF THE CONTENT OF A FUSE MEMORY

SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...

TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES

LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME

INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING

Diagnostic Device

METHOD AND SYSTEM FOR TRACKING AND MANAGING ACTIVITIES OF TESTBENCH...

TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

ERROR PROTECTION ANALYSIS OF AN INTEGRATED CIRCUIT

Scan Chain Analysis Using Predefined Capture Signature

COMPRESSION-BASED SCAN TEST SYSTEM

D FLIP-FLOP HAVING MULTIPLEXER FUNCTION

CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION

ELECTRONIC CIRCUIT AND METHOD OF ERROR CORRECTION

ADDRESSABLE TEST ACCESS PORT

MULTIPLEXER FOR SDFQ HAVING DIFFERENTLY-SIZED SCAN AND DATA TRANSIS...

SERIAL TEST CIRCUIT FOR CONTROLLABLE CHIPLETS

MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS

ARRAY OF UNIT CELLS HAVING PAD STRUCTURES

GLITCH FILTER

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS