Reconfiguring for testing

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CPC
G01R31/3185

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/3185Reconfiguring for testing

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Multi-partition, multi-domain system-on-chip joint test action grou...
- Patent number 12,326,474
- Issue date Jun 10, 2025
- NXP USA, INC.
- Roderick Lee Dorris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic fuse device and operation method thereof
- Patent number 12,326,473
- Issue date Jun 10, 2025
- Faraday Technology Corp.
- Chi-Chou Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Test device for testing on-chip clock controller having debug function
- Patent number 12,320,847
- Issue date Jun 3, 2025
- Realtek Semiconductor Corporation
- Sheng-Ping Yung
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale active thermal interposer for device testing
- Patent number 12,320,841
- Issue date Jun 3, 2025
- ADVANTEST TEST SOLUTIONS, INC.
- Samer Kabbani
- F28 - HEAT EXCHANGE IN GENERAL
Information Patent Grant
High throughput sort
- Patent number 12,320,845
- Issue date Jun 3, 2025
- Infineon Technologies AG
- David Addison
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic voltage frequency scaling to reduce test time
- Patent number 12,320,850
- Issue date Jun 3, 2025
- Mediatek Inc.
- Anshul Varma
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 12,313,667
- Issue date May 27, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Automatic test pattern generation-based circuit verification method...
- Patent number 12,313,680
- Issue date May 27, 2025
- Huawei Technologies Co., Ltd.
- Huiling Zhen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan chains with multi-bit cells and methods for testing the same
- Patent number 12,306,248
- Issue date May 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mohammed Moiz Khan
- G01 - MEASURING TESTING
Information Patent Grant
Saving and restoring scan states
- Patent number 12,306,249
- Issue date May 20, 2025
- Atmosic Technologies, Inc.
- Mohsen Shaaban
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit in chip and circuit test method
- Patent number 12,306,244
- Issue date May 20, 2025
- Huawei Technologies Co., Ltd.
- Yu Huang
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit, an apparatus for testing an integrated circuit,...
- Patent number 12,306,250
- Issue date May 20, 2025
- Advantest Corporation
- Frank Mielke
- G01 - MEASURING TESTING
Information Patent Grant
Secured scan access for a device including a scan chain
- Patent number 12,298,346
- Issue date May 13, 2025
- Texas Instruments Incorporated
- Mudasir Kawoosa
- G01 - MEASURING TESTING
Information Patent Grant
Flip-flop device and method of operating flip-flop device
- Patent number 12,301,228
- Issue date May 13, 2025
- Taiwan Semiconductor Manufacturing Company Ltd.
- Greg Gruber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data gating using scan enable pin
- Patent number 12,287,370
- Issue date Apr 29, 2025
- Apple Inc.
- FNU Rajeev Kumar
- G01 - MEASURING TESTING
Information Patent Grant
Self-correcting circuitry
- Patent number 12,287,369
- Issue date Apr 29, 2025
- Cadence Design Systems, Inc.
- Patrick Murphy
- G01 - MEASURING TESTING
Information Patent Grant
Component die validation built-in self-test (VBIST) engine
- Patent number 12,282,064
- Issue date Apr 22, 2025
- Ampere Computing LLC
- Sandeep Brahmadathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan chain formation for improving chain resolution
- Patent number 12,282,063
- Issue date Apr 22, 2025
- Synopsys, Inc.
- Emil Gizdarski
- G01 - MEASURING TESTING
Information Patent Grant
Testing system and testing method
- Patent number 12,276,698
- Issue date Apr 15, 2025
- ASMedia Technology Inc.
- Te-Ming Kung
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device including through-package debug features
- Patent number 12,272,609
- Issue date Apr 8, 2025
- SanDisk Technologies, Inc.
- Nir Amir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Universal test chiplet
- Patent number 12,265,123
- Issue date Apr 1, 2025
- Nanjing University Of Posts And Telecommunications
- Zhikuang Cai
- G01 - MEASURING TESTING
Information Patent Grant
Compression-based scan test system
- Patent number 12,265,121
- Issue date Apr 1, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Processing system, related integrated circuit, device and method
- Patent number 12,253,562
- Issue date Mar 18, 2025
- STMicroelectronics Application GmbH
- Roberto Colombo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for testing semiconductor circuits
- Patent number 12,241,932
- Issue date Mar 4, 2025
- Ampere Computing LLC
- Kha Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
At-speed test of functional memory interface logic in devices
- Patent number 12,243,603
- Issue date Mar 4, 2025
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit margin measurement for structural testing
- Patent number 12,241,933
- Issue date Mar 4, 2025
- PROTEANTECS LTD.
- Evelyn Landman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital power on reset circuit and method
- Patent number 12,231,116
- Issue date Feb 18, 2025
- Ciena Corporation
- Daryl Anthony Boyd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Photonic wafer level testing systems, devices, and methods of opera...
- Patent number 12,216,020
- Issue date Feb 4, 2025
- STMicroelectronics S.r.l.
- Marco Piazza
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain analysis using predefined capture signature
- Patent number 12,216,161
- Issue date Feb 4, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Grant
Performing scan data transfer inside multi-die package with serdes...
- Patent number 12,216,162
- Issue date Feb 4, 2025
- Advanced Micro Devices, Inc.
- Ahmet Tokuz
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOCK-UP LATCH FOR DUAL-EDGE-TRIGGERED FLIP-FLOPS
- Publication number 20250192757
- Publication date Jun 12, 2025
- QUALCOMM Incorporated
- Yimai PENG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
JTAG STANDARD PIN TEST SYSTEM
- Publication number 20250189581
- Publication date Jun 12, 2025
- SQ TECHNOLOGY (SHANGHAI) CORPORATION
- Qiu-Yue DUAN
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR CIRCUITS
- Publication number 20250189580
- Publication date Jun 12, 2025
- Ampere Computing LLC
- Kha NGUYEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-FUNCTIONAL DETECTION SYSTEM FOR TAP CONTROLLER AND METHOD THEREOF
- Publication number 20250189582
- Publication date Jun 12, 2025
- SQ Technology ( Shanghai ) Corporation
- Xue-Shan Han
- G01 - MEASURING TESTING
Information Patent Application
MODULAR SCAN DATA NETWORK FOR HIGH SPEED SCAN DATA TRANSFER
- Publication number 20250180645
- Publication date Jun 5, 2025
- QUALCOMM Incorporated
- Jais ABRAHAM
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR DEVICE, TEST APPARATUS AND METHOD FOR TESTING SEMICON...
- Publication number 20250164533
- Publication date May 22, 2025
- SK HYNIX INC.
- Chul Hee OH
- G01 - MEASURING TESTING
Information Patent Application
DEVICE ACCESS PORT SELECTION
- Publication number 20250155502
- Publication date May 15, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TESTING CIRCUIT
- Publication number 20250155503
- Publication date May 15, 2025
- GLOBAL UNICHIP CORPORATION
- Yu-Lun Wan
- G01 - MEASURING TESTING
Information Patent Application
CHIP TESTING METHOD AND APPARATUS
- Publication number 20250147101
- Publication date May 8, 2025
- XIAMEN INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE CO., LTD.
- Yonghong HUANG
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20250130278
- Publication date Apr 24, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE ACTIVE THERMAL INTERPOSER FOR DEVICE TESTING
- Publication number 20250130276
- Publication date Apr 24, 2025
- ADVANTEST TEST SOLUTIONS, INC.
- Samer Kabbani
- F28 - HEAT EXCHANGE IN GENERAL
Information Patent Application
DESIGN FOR TEST SCANNING FOR LIGHT-EMITTING DIODE PACKAGES AND RELA...
- Publication number 20250123330
- Publication date Apr 17, 2025
- CreeLED, Inc.
- Christopher P. Hussell
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR AUTOMATED DATA RETRIEVAL FROM AN INTEGRATED CIRCUIT FOR...
- Publication number 20250123329
- Publication date Apr 17, 2025
- NVIDIA Corporation
- Padmanabham Patki
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR GENERATING CLOCK PULSES FOR AT-SPEED TESTING...
- Publication number 20250116703
- Publication date Apr 10, 2025
- NXP B.V.
- Chandan Gupta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHOTONIC WAFER LEVEL TESTING SYSTEMS, DEVICES, AND METHODS OF OPERA...
- Publication number 20250116570
- Publication date Apr 10, 2025
- STMicroelectronics S.r.l.
- Marco Piazza
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS TO DETECT COMPUTING SYSTEM HARDWARE DEFECTS US...
- Publication number 20250110175
- Publication date Apr 3, 2025
- Intel Corporation
- Rakesh KANDULA
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20250102569
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Scan Data Transfer Circuits for Multi-die Chip Testing
- Publication number 20250093416
- Publication date Mar 20, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Application
BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD
- Publication number 20250096783
- Publication date Mar 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
THROUGH-SILICON VIA (TSV) TESTING
- Publication number 20250093404
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUSES AND METHODS FOR FACILIATATING A DYNAMIC CLOCK FREQUENCY...
- Publication number 20250085344
- Publication date Mar 13, 2025
- NXP B.V.
- CHANDAN GUPTA
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAS
- Publication number 20250087539
- Publication date Mar 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DATA CORRECTION AND PHASE OPTIMIZATION IN HIGH-SPEED RECEIVERS
- Publication number 20250085345
- Publication date Mar 13, 2025
- DIODES INCORPORATED
- Yu-Wei Lin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MERGED PARAMETRIC SCAN TOPOLOGY
- Publication number 20250085346
- Publication date Mar 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhishek Chaudhary
- G01 - MEASURING TESTING
Information Patent Application
COMMANDED JTAG TEST ACCESS PORT OPERATIONS
- Publication number 20250085343
- Publication date Mar 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-THROUGHPUT SCAN ARCHITECTURE
- Publication number 20250076380
- Publication date Mar 6, 2025
- Google LLC
- Syed Shakir Iqbal
- G01 - MEASURING TESTING
Information Patent Application
EYE-DIAGRAM INDEX ANALYTIC METHOD, COMPUTER READABLE RECORDING MEDI...
- Publication number 20250076379
- Publication date Mar 6, 2025
- NOVATEK MICROELECTRONICS CORP.
- Kai Li
- G01 - MEASURING TESTING
Information Patent Application
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
- Publication number 20250052811
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS
- Publication number 20250052813
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Application
Prediction of Failure Probabilities of Chips of a Wafer
- Publication number 20250052814
- Publication date Feb 13, 2025
- ROBERT BOSCH GmbH
- Eric Sebastian Schmidt
- G01 - MEASURING TESTING

Reconfiguring for testing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Multi-partition, multi-domain system-on-chip joint test action grou...

Electronic fuse device and operation method thereof

Test device for testing on-chip clock controller having debug function

Wafer scale active thermal interposer for device testing

High throughput sort

Dynamic voltage frequency scaling to reduce test time

Integrated circuit die test architecture

Automatic test pattern generation-based circuit verification method...

Scan chains with multi-bit cells and methods for testing the same

Saving and restoring scan states

Test circuit in chip and circuit test method

Integrated circuit, an apparatus for testing an integrated circuit,...

Secured scan access for a device including a scan chain

Flip-flop device and method of operating flip-flop device

Data gating using scan enable pin

Self-correcting circuitry

Component die validation built-in self-test (VBIST) engine

Scan chain formation for improving chain resolution

Testing system and testing method

Semiconductor device including through-package debug features

Universal test chiplet

Compression-based scan test system

Processing system, related integrated circuit, device and method

Method and system for testing semiconductor circuits

At-speed test of functional memory interface logic in devices

Integrated circuit margin measurement for structural testing

Digital power on reset circuit and method

Photonic wafer level testing systems, devices, and methods of opera...

Scan chain analysis using predefined capture signature

Performing scan data transfer inside multi-die package with serdes...

Patents Applicationslast 30 patents

LOCK-UP LATCH FOR DUAL-EDGE-TRIGGERED FLIP-FLOPS

JTAG STANDARD PIN TEST SYSTEM

METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR CIRCUITS

SELF-FUNCTIONAL DETECTION SYSTEM FOR TAP CONTROLLER AND METHOD THEREOF

MODULAR SCAN DATA NETWORK FOR HIGH SPEED SCAN DATA TRANSFER

SEMICONDUCTOR DEVICE, TEST APPARATUS AND METHOD FOR TESTING SEMICON...

DEVICE ACCESS PORT SELECTION

TESTING CIRCUIT

CHIP TESTING METHOD AND APPARATUS

AT-SPEED TEST ACCESS PORT OPERATIONS

WAFER SCALE ACTIVE THERMAL INTERPOSER FOR DEVICE TESTING

DESIGN FOR TEST SCANNING FOR LIGHT-EMITTING DIODE PACKAGES AND RELA...

SYSTEM FOR AUTOMATED DATA RETRIEVAL FROM AN INTEGRATED CIRCUIT FOR...

SYSTEM AND METHOD FOR GENERATING CLOCK PULSES FOR AT-SPEED TESTING...

PHOTONIC WAFER LEVEL TESTING SYSTEMS, DEVICES, AND METHODS OF OPERA...

METHOD AND APPARATUS TO DETECT COMPUTING SYSTEM HARDWARE DEFECTS US...

3D TAP & SCAN PORT ARCHITECTURES

Scan Data Transfer Circuits for Multi-die Chip Testing

BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD

THROUGH-SILICON VIA (TSV) TESTING

APPARATUSES AND METHODS FOR FACILIATATING A DYNAMIC CLOCK FREQUENCY...

SCAN TESTABLE THROUGH SILICON VIAS

DATA CORRECTION AND PHASE OPTIMIZATION IN HIGH-SPEED RECEIVERS

MERGED PARAMETRIC SCAN TOPOLOGY

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

HIGH-THROUGHPUT SCAN ARCHITECTURE

EYE-DIAGRAM INDEX ANALYTIC METHOD, COMPUTER READABLE RECORDING MEDI...

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS

Prediction of Failure Probabilities of Chips of a Wafer