Reconfiguring for testing

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CPC
G01R31/3185

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/3185Reconfiguring for testing

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device including through-package debug features
- Patent number 12,272,609
- Issue date Apr 8, 2025
- SanDisk Technologies, Inc.
- Nir Amir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Universal test chiplet
- Patent number 12,265,123
- Issue date Apr 1, 2025
- Nanjing University Of Posts And Telecommunications
- Zhikuang Cai
- G01 - MEASURING TESTING
Information Patent Grant
Compression-based scan test system
- Patent number 12,265,121
- Issue date Apr 1, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Processing system, related integrated circuit, device and method
- Patent number 12,253,562
- Issue date Mar 18, 2025
- STMicroelectronics Application GmbH
- Roberto Colombo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for testing semiconductor circuits
- Patent number 12,241,932
- Issue date Mar 4, 2025
- Ampere Computing LLC
- Kha Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
At-speed test of functional memory interface logic in devices
- Patent number 12,243,603
- Issue date Mar 4, 2025
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit margin measurement for structural testing
- Patent number 12,241,933
- Issue date Mar 4, 2025
- PROTEANTECS LTD.
- Evelyn Landman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital power on reset circuit and method
- Patent number 12,231,116
- Issue date Feb 18, 2025
- Ciena Corporation
- Daryl Anthony Boyd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Photonic wafer level testing systems, devices, and methods of opera...
- Patent number 12,216,020
- Issue date Feb 4, 2025
- STMicroelectronics S.r.l.
- Marco Piazza
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain analysis using predefined capture signature
- Patent number 12,216,161
- Issue date Feb 4, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Grant
Performing scan data transfer inside multi-die package with serdes...
- Patent number 12,216,162
- Issue date Feb 4, 2025
- Advanced Micro Devices, Inc.
- Ahmet Tokuz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die aging measurements for dynamic timing modeling
- Patent number 12,216,150
- Issue date Feb 4, 2025
- Altera Corporation
- Dheeraj Subbareddy
- G01 - MEASURING TESTING
Information Patent Grant
Device access port selection
- Patent number 12,210,060
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Wafer level methods of testing semiconductor devices using internal...
- Patent number 12,203,980
- Issue date Jan 21, 2025
- Samsung Electronics Co., Ltd.
- Ahn Choi
- G01 - MEASURING TESTING
Information Patent Grant
Test-time optimization with few slow scan pads
- Patent number 12,203,985
- Issue date Jan 21, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain circuit and corresponding method
- Patent number 12,203,984
- Issue date Jan 21, 2025
- STMicroelectronics S.r.l.
- Marco Casarsa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Diagnostic device
- Patent number 12,203,981
- Issue date Jan 21, 2025
- The Boeing Company
- Ian M. Dayton
- G01 - MEASURING TESTING
Information Patent Grant
Test method of storage device implemented in multi-chip package (MC...
- Patent number 12,205,852
- Issue date Jan 21, 2025
- Samsung Electronics Co., Ltd.
- Sangmin An
- G11 - INFORMATION STORAGE
Information Patent Grant
Error protection analysis of an integrated circuit
- Patent number 12,188,979
- Issue date Jan 7, 2025
- International Business Machines Corporation
- Benjamin Neil Trombley
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for post-binding testing of 2.5D chiplet
- Patent number 12,188,984
- Issue date Jan 7, 2025
- Nanjing University Of Posts And Telecommunications
- Zhikuang Cai
- G01 - MEASURING TESTING
Information Patent Grant
Test access port with address and command capability
- Patent number 12,188,980
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit having test circuitry for memory sub-systems
- Patent number 12,181,522
- Issue date Dec 31, 2024
- NXP USA, INC.
- Alexander Hoefler
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed test access port operations
- Patent number 12,181,521
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data correction and phase optimization in high-speed receivers
- Patent number 12,181,523
- Issue date Dec 31, 2024
- Diodes Incorporated
- Yu-Wei Lin
- G01 - MEASURING TESTING
Information Patent Grant
Chip test circuit and circuit test method
- Patent number 12,181,519
- Issue date Dec 31, 2024
- Huawei Technologies Co., Ltd.
- Changming Cui
- G01 - MEASURING TESTING
Information Patent Grant
System testing using partitioned and controlled noise
- Patent number 12,174,251
- Issue date Dec 24, 2024
- International Business Machines Corporation
- Mary P. Kusko
- G01 - MEASURING TESTING
Information Patent Grant
Fault detection method and related apparatus
- Patent number 12,174,254
- Issue date Dec 24, 2024
- Huawei Technologies Co., Ltd.
- Zhe Tao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TSV testing
- Patent number 12,163,998
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bi-directional scan flip-flop circuit and method
- Patent number 12,166,487
- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Huaixin Xian
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR GENERATING CLOCK PULSES FOR AT-SPEED TESTING...
- Publication number 20250116703
- Publication date Apr 10, 2025
- NXP B.V.
- Chandan Gupta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHOTONIC WAFER LEVEL TESTING SYSTEMS, DEVICES, AND METHODS OF OPERA...
- Publication number 20250116570
- Publication date Apr 10, 2025
- STMicroelectronics S.r.l.
- Marco Piazza
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS TO DETECT COMPUTING SYSTEM HARDWARE DEFECTS US...
- Publication number 20250110175
- Publication date Apr 3, 2025
- Intel Corporation
- Rakesh KANDULA
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20250102569
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Scan Data Transfer Circuits for Multi-die Chip Testing
- Publication number 20250093416
- Publication date Mar 20, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Application
BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD
- Publication number 20250096783
- Publication date Mar 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Huaixin XIAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
THROUGH-SILICON VIA (TSV) TESTING
- Publication number 20250093404
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUSES AND METHODS FOR FACILIATATING A DYNAMIC CLOCK FREQUENCY...
- Publication number 20250085344
- Publication date Mar 13, 2025
- NXP B.V.
- CHANDAN GUPTA
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAS
- Publication number 20250087539
- Publication date Mar 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DATA CORRECTION AND PHASE OPTIMIZATION IN HIGH-SPEED RECEIVERS
- Publication number 20250085345
- Publication date Mar 13, 2025
- DIODES INCORPORATED
- Yu-Wei Lin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MERGED PARAMETRIC SCAN TOPOLOGY
- Publication number 20250085346
- Publication date Mar 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhishek Chaudhary
- G01 - MEASURING TESTING
Information Patent Application
COMMANDED JTAG TEST ACCESS PORT OPERATIONS
- Publication number 20250085343
- Publication date Mar 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-THROUGHPUT SCAN ARCHITECTURE
- Publication number 20250076380
- Publication date Mar 6, 2025
- Google LLC
- Syed Shakir Iqbal
- G01 - MEASURING TESTING
Information Patent Application
EYE-DIAGRAM INDEX ANALYTIC METHOD, COMPUTER READABLE RECORDING MEDI...
- Publication number 20250076379
- Publication date Mar 6, 2025
- NOVATEK MICROELECTRONICS CORP.
- Kai Li
- G01 - MEASURING TESTING
Information Patent Application
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
- Publication number 20250052811
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS
- Publication number 20250052813
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Application
Prediction of Failure Probabilities of Chips of a Wafer
- Publication number 20250052814
- Publication date Feb 13, 2025
- ROBERT BOSCH GmbH
- Eric Sebastian Schmidt
- G01 - MEASURING TESTING
Information Patent Application
SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION
- Publication number 20250035703
- Publication date Jan 30, 2025
- STMicroelectronics International N.V.
- Ankur BAL
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO...
- Publication number 20250027993
- Publication date Jan 23, 2025
- QUALCOMM Incorporated
- Paul POLICKE
- G01 - MEASURING TESTING
Information Patent Application
MONITOR CIRCUIT TO DETERMINE INTEGRATED CIRCUIT CONDITION BASED ON...
- Publication number 20250027996
- Publication date Jan 23, 2025
- QUALCOMM Incorporated
- Anatoly GELMAN
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING
- Publication number 20250027992
- Publication date Jan 23, 2025
- Samsung Electronics Co., Ltd.
- Seaeun Park
- G01 - MEASURING TESTING
Information Patent Application
TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS
- Publication number 20250027994
- Publication date Jan 23, 2025
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS
- Publication number 20250027995
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Arnab Khawas
- G01 - MEASURING TESTING
Information Patent Application
ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHOD
- Publication number 20250020718
- Publication date Jan 16, 2025
- Anritsu Corporation
- Hironori YOSHIOKA
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME
- Publication number 20250020719
- Publication date Jan 16, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mohammed Moiz Khan
- G01 - MEASURING TESTING
Information Patent Application
PROTECTION OF THE CONTENT OF A FUSE MEMORY
- Publication number 20250004051
- Publication date Jan 2, 2025
- STMicroelectronics (Grenoble 2) SAS
- Mark Trimmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...
- Publication number 20240426908
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Andrea Floridia
- G01 - MEASURING TESTING
Information Patent Application
TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES
- Publication number 20240426907
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Shiv Kumar Vats
- G01 - MEASURING TESTING
Information Patent Application
LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME
- Publication number 20240426909
- Publication date Dec 26, 2024
- SAMSUNG ELECTRONICS CO,. LTD.
- Sangsoon IM
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING
- Publication number 20240418776
- Publication date Dec 19, 2024
- NORDIC SEMICONDUCTOR ASA
- Ashraf MOHAMMED
- G01 - MEASURING TESTING

Reconfiguring for testing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor device including through-package debug features

Universal test chiplet

Compression-based scan test system

Processing system, related integrated circuit, device and method

Method and system for testing semiconductor circuits

At-speed test of functional memory interface logic in devices

Integrated circuit margin measurement for structural testing

Digital power on reset circuit and method

Photonic wafer level testing systems, devices, and methods of opera...

Scan chain analysis using predefined capture signature

Performing scan data transfer inside multi-die package with serdes...

On-die aging measurements for dynamic timing modeling

Device access port selection

Wafer level methods of testing semiconductor devices using internal...

Test-time optimization with few slow scan pads

Scan chain circuit and corresponding method

Diagnostic device

Test method of storage device implemented in multi-chip package (MC...

Error protection analysis of an integrated circuit

Circuit and method for post-binding testing of 2.5D chiplet

Test access port with address and command capability

Integrated circuit having test circuitry for memory sub-systems

At-speed test access port operations

Data correction and phase optimization in high-speed receivers

Chip test circuit and circuit test method

System testing using partitioned and controlled noise

Fault detection method and related apparatus

3D tap and scan port architectures

TSV testing

Bi-directional scan flip-flop circuit and method

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR GENERATING CLOCK PULSES FOR AT-SPEED TESTING...

PHOTONIC WAFER LEVEL TESTING SYSTEMS, DEVICES, AND METHODS OF OPERA...

METHOD AND APPARATUS TO DETECT COMPUTING SYSTEM HARDWARE DEFECTS US...

3D TAP & SCAN PORT ARCHITECTURES

Scan Data Transfer Circuits for Multi-die Chip Testing

BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD

THROUGH-SILICON VIA (TSV) TESTING

APPARATUSES AND METHODS FOR FACILIATATING A DYNAMIC CLOCK FREQUENCY...

SCAN TESTABLE THROUGH SILICON VIAS

DATA CORRECTION AND PHASE OPTIMIZATION IN HIGH-SPEED RECEIVERS

MERGED PARAMETRIC SCAN TOPOLOGY

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

HIGH-THROUGHPUT SCAN ARCHITECTURE

EYE-DIAGRAM INDEX ANALYTIC METHOD, COMPUTER READABLE RECORDING MEDI...

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS

Prediction of Failure Probabilities of Chips of a Wafer

SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION

INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO...

MONITOR CIRCUIT TO DETERMINE INTEGRATED CIRCUIT CONDITION BASED ON...

INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING

TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS

CLOCK GATING CIRCUITS AND METHODS FOR DUAL-EDGE-TRIGGERED APPLICATIONS

ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHOD

SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME

PROTECTION OF THE CONTENT OF A FUSE MEMORY

SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...

TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES

LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME

INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING