Test of counters

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CPC
G01R31/318527

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/318527Test of counters

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Apparatus, system, and method for achieving accurate insertion coun...
- Patent number 11,901,898
- Issue date Feb 13, 2024
- Juniper Networks, Inc.
- John Kenney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fail-safe counter evaluator to insure proper counting by a counter
- Patent number 11,824,535
- Issue date Nov 21, 2023
- Siemens Aktiengesellschaft
- Steven Parfitt
- G01 - MEASURING TESTING
Information Patent Grant
Multi-capture at-speed scan test based on a slow clock signal
- Patent number 11,614,487
- Issue date Mar 28, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Grant
Runtime measurement of process variations and supply voltage charac...
- Patent number 11,585,854
- Issue date Feb 21, 2023
- Xilinx, Inc.
- Da Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for achieving accurate insertion coun...
- Patent number 11,489,528
- Issue date Nov 1, 2022
- Juniper Networks, Inc.
- John Kenney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Eye diagram measurement device and eye diagram measurement method
- Patent number 10,735,149
- Issue date Aug 4, 2020
- Global Unichip Corporation
- Wen-Juh Kang
- G01 - MEASURING TESTING
Information Patent Grant
Detection of a digital counter malfunction
- Patent number 7,688,932
- Issue date Mar 30, 2010
- STMicroelectronics S.A.
- Philippe Roquelaure
- G01 - MEASURING TESTING
Information Patent Grant
Built-in self test for a counter system
- Patent number 6,975,696
- Issue date Dec 13, 2005
- STMicroelectronics, Inc.
- Naren K. Sahoo
- G01 - MEASURING TESTING
Information Patent Grant
Ripple counter circuits and methods providing improved self-testing...
- Patent number 6,853,698
- Issue date Feb 8, 2005
- Xilinx, Inc.
- Andy T. Nguyen
- G01 - MEASURING TESTING
Information Patent Grant
BIST circuit for variable impedance system
- Patent number 6,509,778
- Issue date Jan 21, 2003
- International Business Machines Corporation
- George M Braceras
- G01 - MEASURING TESTING
Information Patent Grant
Command generator having single-input to multi-output converter
- Patent number 6,314,537
- Issue date Nov 6, 2001
- Hyundai Electronics Industries Co., Ltd.
- Young-Nam Oh
- G01 - MEASURING TESTING
Information Patent Grant
Counting apparatus and rotation stopped detection apparatus which u...
- Patent number 6,292,524
- Issue date Sep 18, 2001
- The Nippon Signal Co., Ltd.
- Masayoshi Sakai
- G01 - MEASURING TESTING
Information Patent Grant
Counter and a revolution stop detection apparatus using the counter
- Patent number 6,148,055
- Issue date Nov 14, 2000
- The Nippon Signal Co., Ltd.
- Masayoshi Sakai
- G01 - MEASURING TESTING
Information Patent Grant
Method for concurrent testing of on-chip circuitry and timing counters
- Patent number 6,085,343
- Issue date Jul 4, 2000
- Sun Microsystems, Inc.
- Suresh Krishnamoorthy
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor integrated circuit device and its test method
- Patent number 5,991,906
- Issue date Nov 23, 1999
- Kabushiki Kaisha Toshiba
- Tsuneyuki Hashimoto
- G01 - MEASURING TESTING
Information Patent Grant
Low power scannable counter
- Patent number 5,960,052
- Issue date Sep 28, 1999
- VLSI Technology, Inc.
- Jerome Bombal
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing counter and serial access memory
- Patent number 5,930,186
- Issue date Jul 27, 1999
- Oki Electric Industry Co., Ltd.
- Itsuro Iwakiri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to determine erroneous value in memory cells u...
- Patent number 5,761,213
- Issue date Jun 2, 1998
- International Business Machines Corporation
- Robert Dean Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rapid compare of two binary numbers
- Patent number 5,745,498
- Issue date Apr 28, 1998
- International Business Machines Corporation
- Robert Dean Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital counter test circuit
- Patent number 5,740,219
- Issue date Apr 14, 1998
- VLSI Technology, Inc.
- David John O'Dell
- G01 - MEASURING TESTING
Information Patent Grant
Testable high count counter
- Patent number 5,694,444
- Issue date Dec 2, 1997
- Lucent Technologies Inc.
- Sonali Bagchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic division system and method for improving testability of a c...
- Patent number 5,651,040
- Issue date Jul 22, 1997
- VLSI Technology, Inc.
- Tein-Yow Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
BIST tester for multiple memories
- Patent number 5,535,164
- Issue date Jul 9, 1996
- International Business Machines Corporation
- Robert D. Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing long counters
- Patent number 5,481,580
- Issue date Jan 2, 1996
- AT&T Corp.
- Miroslaw Guzinski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for testing counter circuit
- Patent number 5,479,412
- Issue date Dec 26, 1995
- NEC Corporation
- Toshio Enomoto
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing large embedded counters
- Patent number 5,473,651
- Issue date Dec 5, 1995
- AT&T Corp.
- Miroslaw Guzinski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transparent testing of integrated circuits
- Patent number 5,469,445
- Issue date Nov 21, 1995
- Sofia Koloni Ltd.
- Michael Nicolaidis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo-random vector generated testable counter
- Patent number 5,412,580
- Issue date May 2, 1995
- Hughes Aircraft Company
- James L. Fulcomer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to accelerate counter testing without loss of fault coverage
- Patent number 5,402,458
- Issue date Mar 28, 1995
- Cyrix Corporation
- Claude Moughanni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient functional test scheme incorporated in a programmable dur...
- Patent number 5,381,453
- Issue date Jan 10, 1995
- Zilog, Inc.
- Stephen H. Chan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS, SYSTEM, AND METHOD FOR ACHIEVING ACCURATE INSERTION COUN...
- Publication number 20230134891
- Publication date May 4, 2023
- Juniper Networks, Inc.
- John Kenney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A SCALABLE DIGITAL INFRASTRUC...
- Publication number 20220413045
- Publication date Dec 29, 2022
- IC ANALYTICA, LLC
- Richard WUNDERLICH
- G01 - MEASURING TESTING
Information Patent Application
MULTI-CAPTURE AT-SPEED SCAN TEST BASED ON A SLOW CLOCK SIGNAL
- Publication number 20220018902
- Publication date Jan 20, 2022
- Siemens Industry Software Inc.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
FAIL-SAFE COUNTER EVALUATOR TO INSURE PROPER COUNTING BY A COUNTER
- Publication number 20210258012
- Publication date Aug 19, 2021
- Siemens Industry, Inc.
- Steven Parfitt
- G01 - MEASURING TESTING
Information Patent Application
EYE DIAGRAM MEASUREMENT DEVICE AND EYE DIAGRAM MEASUREMENT METHOD
- Publication number 20200014501
- Publication date Jan 9, 2020
- Global Unichip Corporation
- Wen-Juh KANG
- G01 - MEASURING TESTING
Information Patent Application
DETECTION OF A DIGITAL COUNTER MALFUNCTION
- Publication number 20080165913
- Publication date Jul 10, 2008
- STMicroelectronics S.A.
- Philippe Roquelaure
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BIST circuit for variable impedance system
- Publication number 20020130697
- Publication date Sep 19, 2002
- International Business Machines Corporation
- George M. Braceras
- G01 - MEASURING TESTING

Test of counters

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Apparatus, system, and method for achieving accurate insertion coun...

Fail-safe counter evaluator to insure proper counting by a counter

Multi-capture at-speed scan test based on a slow clock signal

Runtime measurement of process variations and supply voltage charac...

Apparatus, system, and method for achieving accurate insertion coun...

Eye diagram measurement device and eye diagram measurement method

Detection of a digital counter malfunction

Built-in self test for a counter system

Ripple counter circuits and methods providing improved self-testing...

BIST circuit for variable impedance system

Command generator having single-input to multi-output converter

Counting apparatus and rotation stopped detection apparatus which u...

Counter and a revolution stop detection apparatus using the counter

Method for concurrent testing of on-chip circuitry and timing counters

Semiconductor integrated circuit device and its test method

Low power scannable counter

Method and apparatus for testing counter and serial access memory

Method and apparatus to determine erroneous value in memory cells u...

Rapid compare of two binary numbers

Digital counter test circuit

Testable high count counter

Dynamic division system and method for improving testability of a c...

BIST tester for multiple memories

Method and apparatus for testing long counters

Apparatus for testing counter circuit

Method and apparatus for testing large embedded counters

Transparent testing of integrated circuits

Pseudo-random vector generated testable counter

Mechanism to accelerate counter testing without loss of fault coverage

Efficient functional test scheme incorporated in a programmable dur...

Patents Applicationslast 30 patents

APPARATUS, SYSTEM, AND METHOD FOR ACHIEVING ACCURATE INSERTION COUN...

APPARATUS AND METHOD FOR IMPLEMENTING A SCALABLE DIGITAL INFRASTRUC...

MULTI-CAPTURE AT-SPEED SCAN TEST BASED ON A SLOW CLOCK SIGNAL

FAIL-SAFE COUNTER EVALUATOR TO INSURE PROPER COUNTING BY A COUNTER

EYE DIAGRAM MEASUREMENT DEVICE AND EYE DIAGRAM MEASUREMENT METHOD

DETECTION OF A DIGITAL COUNTER MALFUNCTION

BIST circuit for variable impedance system