Test of Multi-Chip-Moduls

Industry

CPC
G01R31/318513

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Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318513Test of Multi-Chip-Moduls

Industries

Patents Grantslast 30 patents

Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan testable through silicon VIAs
- Patent number 12,154,835
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cost-saving scheme for scan testing of 3D stack die
- Patent number 12,099,091
- Issue date Sep 24, 2024
- Advanced Micro Devices, Inc.
- Songgan Zang
- G01 - MEASURING TESTING
Information Patent Grant
Built in self-test of heterogeneous integrated radio frequency chip...
- Patent number 12,099,092
- Issue date Sep 24, 2024
- PseudolithIC, Inc.
- James Buckwalter
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 12,025,649
- Issue date Jul 2, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
3D stacked die test architecture
- Patent number 12,007,441
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit including test circuit and method of manufacturi...
- Patent number 12,000,888
- Issue date Jun 4, 2024
- Samsung Electronics Co., Ltd.
- Changho Han
- G01 - MEASURING TESTING
Information Patent Grant
Built in self-test of heterogeneous integrated radio frequency chip...
- Patent number 11,940,495
- Issue date Mar 26, 2024
- PseudolithIC, Inc.
- James Buckwalter
- G01 - MEASURING TESTING
Information Patent Grant
System and method for schedule-based I/O multiplexing for integrate...
- Patent number 11,927,630
- Issue date Mar 12, 2024
- MARVELL ASIA PTE. LTD.
- Sounil Biswas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 11,899,064
- Issue date Feb 13, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
Identifying causes of anomalies observed in an integrated circuit chip
- Patent number 11,816,016
- Issue date Nov 14, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Gajinder Panesar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method of monitoring chip process variation and perfo...
- Patent number 11,789,076
- Issue date Oct 17, 2023
- Mediatek Inc.
- Ko-Ching Su
- G01 - MEASURING TESTING
Information Patent Grant
3D TAP and scan port architectures
- Patent number 11,762,014
- Issue date Sep 19, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Built in self-test of heterogeneous integrated radio frequency chip...
- Patent number 11,733,297
- Issue date Aug 22, 2023
- PseudolithIC, Inc.
- James Buckwaiter
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 11,726,135
- Issue date Aug 15, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Automatic test pattern generation circuitry in multi power domain s...
- Patent number 11,680,982
- Issue date Jun 20, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D stacked die test architecture
- Patent number 11,675,007
- Issue date Jun 13, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Chip testing apparatus and system with sharing test interface
- Patent number 11,630,153
- Issue date Apr 18, 2023
- Winbond Electronics Corp.
- Chih-Chiang Lai
- G11 - INFORMATION STORAGE
Information Patent Grant
Test system and probe device
- Patent number 11,598,807
- Issue date Mar 7, 2023
- Kioxia Corporation
- Masayuki Oishi
- G01 - MEASURING TESTING
Information Patent Grant
Testing holders for chip unit and die package
- Patent number 11,579,190
- Issue date Feb 14, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Scan architecture for interconnect testing in 3D integrated circuits
- Patent number 11,549,984
- Issue date Jan 10, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sandeep Kumar Goel
- G01 - MEASURING TESTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 11,549,983
- Issue date Jan 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scalable infield scan coverage for multi-chip module for functional...
- Patent number 11,506,702
- Issue date Nov 22, 2022
- Intel Corporation
- Asad Azam
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor chips including through electrodes and methods of tes...
- Patent number 11,476,169
- Issue date Oct 18, 2022
- SK hynix Inc.
- Sun Myung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D stacked die test architecture
- Patent number 11,428,736
- Issue date Aug 30, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Probe card having dummy traces for testing an integrated circuit to...
- Patent number 11,422,155
- Issue date Aug 23, 2022
- MELLANOX TECHNOLOGIES, LTD.
- Konstantin Turchin
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 11,391,769
- Issue date Jul 19, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Testing holders for chip unit and die package
- Patent number 11,340,291
- Issue date May 24, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Grant
Scan testable through silicon VIAs
- Patent number 11,302,591
- Issue date Apr 12, 2022
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alignment testing for tiered semiconductor structure
- Patent number 11,231,453
- Issue date Jan 25, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Mill-Jer Wang
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20240345154
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
BUILT IN SELF-TEST OF HETEROGENEOUS INTEGRATED RADIO FREQUENCY CHIP...
- Publication number 20240329136
- Publication date Oct 3, 2024
- PseudolithIC, Inc.
- James Buckwalter
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20240319274
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20240133951
- Publication date Apr 25, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230417831
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20230366920
- Publication date Nov 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230160958
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20230113905
- Publication date Apr 13, 2023
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
IDENTIFYING CAUSES OF ANOMALIES OBSERVED IN AN INTEGRATED CIRCUIT CHIP
- Publication number 20230004471
- Publication date Jan 5, 2023
- Siemens Industry Software Inc.
- Gajinder Panesar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20220381821
- Publication date Dec 1, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20220341985
- Publication date Oct 27, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
CHIP TESTING APPARATUS AND SYSTEM
- Publication number 20220341991
- Publication date Oct 27, 2022
- WINBOND ELECTRONICS CORP.
- Chih-Chiang Lai
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE
- Publication number 20220283221
- Publication date Sep 8, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mill-Jer Wang
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAs
- Publication number 20220230928
- Publication date Jul 21, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20220107362
- Publication date Apr 7, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST METHOD OF STORAGE DEVICE IMPLEMENTED IN MULTI-CHIP PACKAGE (MC...
- Publication number 20220102224
- Publication date Mar 31, 2022
- Samsung Electronics Co., Ltd.
- Sangmin AN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEST SYSTEM AND PROBE DEVICE
- Publication number 20220082622
- Publication date Mar 17, 2022
- KIOXIA Corporation
- Masayuki OISHI
- G01 - MEASURING TESTING
Information Patent Application
Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Withou...
- Publication number 20210333326
- Publication date Oct 28, 2021
- Peter Shun Shen Wang
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20210270895
- Publication date Sep 2, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
DIE STACK TEST ARCHITECTURE AND METHOD
- Publication number 20210148963
- Publication date May 20, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD OF MONITORING CHIP PROCESS VARIATION AND PERFO...
- Publication number 20210141016
- Publication date May 13, 2021
- MEDIATEK INC.
- Ko-Ching Su
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20210088587
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCALABLE INFIELD SCAN COVERAGE FOR MULTI-CHIP MODULE FOR FUCTIONAL...
- Publication number 20210003629
- Publication date Jan 7, 2021
- Intel Corporation
- Asad Azam
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAs
- Publication number 20200411394
- Publication date Dec 31, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Probe Card for Testing a Die to Be Installed in a Multichip-Module
- Publication number 20200379006
- Publication date Dec 3, 2020
- MELLANOX TECHNOLOGIES, LTD.
- Konstantin Turchin
- G01 - MEASURING TESTING
Information Patent Application
TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE
- Publication number 20200326370
- Publication date Oct 15, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mill-Jer WANG
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR WAFER
- Publication number 20200174074
- Publication date Jun 4, 2020
- Hamamatsu Photonics K.K.
- Motohiro SUYAMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20200166572
- Publication date May 28, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
- Publication number 20200124668
- Publication date Apr 23, 2020
- Sandeep Kumar GOEL
- G01 - MEASURING TESTING
Information Patent Application
DIE STACK TEST ARCHITECTURE AND METHOD
- Publication number 20200116779
- Publication date Apr 16, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Test of Multi-Chip-Moduls

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

3D tap and scan port architectures

Scan testable through silicon VIAs

Cost-saving scheme for scan testing of 3D stack die

Built in self-test of heterogeneous integrated radio frequency chip...

Integrated circuit die test architecture

3D stacked die test architecture

Integrated circuit including test circuit and method of manufacturi...

Built in self-test of heterogeneous integrated radio frequency chip...

System and method for schedule-based I/O multiplexing for integrate...

Scan architecture for interconnect testing in 3D integrated circuits

Identifying causes of anomalies observed in an integrated circuit chip

Apparatus and method of monitoring chip process variation and perfo...

3D TAP and scan port architectures

Built in self-test of heterogeneous integrated radio frequency chip...

Integrated circuit die test architecture

Automatic test pattern generation circuitry in multi power domain s...

3D stacked die test architecture

Chip testing apparatus and system with sharing test interface

Test system and probe device

Testing holders for chip unit and die package

Scan architecture for interconnect testing in 3D integrated circuits

3D tap and scan port architectures

Scalable infield scan coverage for multi-chip module for functional...

Semiconductor chips including through electrodes and methods of tes...

3D stacked die test architecture

Probe card having dummy traces for testing an integrated circuit to...

Integrated circuit die test architecture

Testing holders for chip unit and die package

Scan testable through silicon VIAs

Alignment testing for tiered semiconductor structure

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

BUILT IN SELF-TEST OF HETEROGENEOUS INTEGRATED RADIO FREQUENCY CHIP...

3D STACKED DIE TEST ARCHITECTURE

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

3D TAP & SCAN PORT ARCHITECTURES

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

3D TAP & SCAN PORT ARCHITECTURES

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

IDENTIFYING CAUSES OF ANOMALIES OBSERVED IN AN INTEGRATED CIRCUIT CHIP

3D STACKED DIE TEST ARCHITECTURE

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

CHIP TESTING APPARATUS AND SYSTEM

TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE

SCAN TESTABLE THROUGH SILICON VIAs

3D TAP & SCAN PORT ARCHITECTURES

TEST METHOD OF STORAGE DEVICE IMPLEMENTED IN MULTI-CHIP PACKAGE (MC...

TEST SYSTEM AND PROBE DEVICE

Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Withou...

3D STACKED DIE TEST ARCHITECTURE

DIE STACK TEST ARCHITECTURE AND METHOD

APPARATUS AND METHOD OF MONITORING CHIP PROCESS VARIATION AND PERFO...

3D TAP & SCAN PORT ARCHITECTURES

SCALABLE INFIELD SCAN COVERAGE FOR MULTI-CHIP MODULE FOR FUCTIONAL...

SCAN TESTABLE THROUGH SILICON VIAs

Probe Card for Testing a Die to Be Installed in a Multichip-Module

TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE

SEMICONDUCTOR WAFER

3D STACKED DIE TEST ARCHITECTURE

SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS

DIE STACK TEST ARCHITECTURE AND METHOD