the chip support structure consisting of a plurality of insulating substrates

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H01L23/49833

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L23/00Details of semiconductor or other solid state devices

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H01L23/49833the chip support structure consisting of a plurality of insulating substrates

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Patents Grantslast 30 patents

Information Patent Grant
Semiconductor package with hybrid mold layers
- Patent number 12,288,740
- Issue date Apr 29, 2025
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
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- Junwoo Park
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Information Patent Grant
Fan-out semiconductor package
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- Joonsung Kim
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
Coplanar control for film-type thermal interface
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- Yu-Hsun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with conductive adhesive that overflows for r...
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
Semiconductor device comprising interconnect structures
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- Issue date Mar 11, 2025
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Information Patent Grant
Electronic device
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- Yoichiro Kurita
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Information Patent Grant
Package structure, RDL structure comprising redistribution layer ha...
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- Issue date Mar 11, 2025
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- Chien-Hsun Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
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Information Patent Grant
3D stack of split graphics processing logic dies
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
Embedded die on interposer packages
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- John S. Guzek
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Information Patent Grant
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- Che-Hung Kuo
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Information Patent Grant
Magnetic core inductors in interposer
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- Issue date Feb 11, 2025
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- Krishna Bharath
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Information Patent Grant
Electronic package including lead frame having multiple conductive...
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- Chih-Hsien Chiu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

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SEMICONDUCTOR PACKAGE WITH A BACKSIDE POWER DISTRIBUTION NETWORK
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SEMICONDUCTOR PACKAGE INCLUDING A CORE LAYER
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SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
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PASSIVATION STRUCTURE WITH PLANAR TOP SURFACES
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- TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
- Yi-Hsiu Chen
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SEMICONDUCTOR PACKAGE WITH A FAN-OUT LEVEL PACKAGE
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- Bongsoo Kim
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SEMICONDUCTOR PACKAGE
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- Samsung Electronics Co., Ltd.
- Kyuhyeon CHOI
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ELECTRONIC DEVICE
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PACKAGE WITH BACK-TO-BACK DIE STACKING
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- Faxing CHE
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CHIP PACKAGE
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SEMICONDUCTOR PACKAGE
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- Samsung Electronics Co., Ltd.
- Jae Sup Lee
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SEMICONDUCTOR PACKAGE
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INTERPOSER CONNECTION STRUCTURES BASED ON WIRE BONDING
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3D CHIP PACKAGE BASED ON VERTICAL-THROUGH-VIA CONNECTOR
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- Yueh-Ting Lin
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Information Patent Application
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- KaiChong CHAN
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- CHUNG-HSIUNG HO
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SEMICONDUCTOR PACKAGE
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- Sang Sub Song
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- Brett P. WILKERSON
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SEMICONDUCTOR PACKAGE
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- SUNJAE KIM
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Information Patent Application
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- Samsung Electronics Co., Ltd.
- Young-Deuk KIM
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Information Patent Application
INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A CAPACITOR-EMBEDDED, RE...
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- QUALCOMM Incorporated
- Jihong Choi
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Information Patent Application
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- Publication number 20250118640
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- SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Atapol PRAJUCKAMOL
- H01 - BASIC ELECTRIC ELEMENTS

the chip support structure consisting of a plurality of insulating substrates

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor package with hybrid mold layers

Semiconductor package

Fan-out semiconductor package

High density interconnection using fanout interposer chiplet

Electronic package and manufacturing method thereof

Substrate frame design for three-dimensional stacked electronic ass...

Coplanar control for film-type thermal interface

Semiconductor package with conductive adhesive that overflows for r...

Semiconductor package having multiple substrates

Semiconductor device package with conductive pillars and reinforcin...

Chip heat dissipating structure, chip structure, circuit board and...

Semiconductor packages including antenna pattern

Semiconductor package having an encapulant comprising conductive fi...

Semiconductor package

Semiconductor package

Secure semiconductor integration and method for making thereof

Semiconductor package including heat dissipation layer

Semiconductor device comprising interconnect structures

Electronic device

Package structure, RDL structure comprising redistribution layer ha...

Manufacturing method of integrated substrate structure

3D stack of split graphics processing logic dies

Semiconductor package and method for fabricating the same

Semiconductor device and manufacturing method thereof

Semiconductor chiplet device

Three-dimensional integrated circuit structures and methods of form...

Embedded die on interposer packages

Semiconductor package structure

Magnetic core inductors in interposer

Electronic package including lead frame having multiple conductive...

Patents Applicationslast 30 patents

ELECTRONIC COMPONENT-INCORPORATING SUBSTRATE

ELECTRONIC DEVICE

ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

ELECTRONIC PACKAGE ASSEMBLY AND METHODS FOR FORMING THE SAME

SEMICONDUCTOR PACKAGE WITH A BACKSIDE POWER DISTRIBUTION NETWORK

SEMICONDUCTOR PACKAGE INCLUDING A CORE LAYER

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

PASSIVATION STRUCTURE WITH PLANAR TOP SURFACES

SEMICONDUCTOR PACKAGE WITH A FAN-OUT LEVEL PACKAGE

SEMICONDUCTOR PACKAGE

ELECTRONIC DEVICE

PACKAGE WITH BACK-TO-BACK DIE STACKING

ELECTRONIC PACKAGE INCLUDING LEAD FRAME HAVING MULTIPLE CONDUCTIVE...

CHIP PACKAGE

SEMICONDUCTOR PACKAGE

SEMICONDUCTOR PACKAGE

INTERPOSER CONNECTION STRUCTURES BASED ON WIRE BONDING

3D CHIP PACKAGE BASED ON VERTICAL-THROUGH-VIA CONNECTOR

PANEL-LEVEL PACKAGED (PLP) INTEGRATED CIRCUITS AND METHODS OF MANUF...

SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH

INTEGRATED PACKAGE AND METHOD FOR MAKING THE SAME

SIDE-WETTABLE PACKAGE WITH EDGE-RECESSED BOND PADS

SEMICONDUCTOR PACKAGE HAVING IMPROVED THERMAL CHARACTERISTICS

SEMICONDUCTOR PACKAGE

CHIP PACKAGE WITH MULTIPLE HBM STACKS

SEMICONDUCTOR PACKAGE

SEMICONDUCTOR PACKAGE

INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A CAPACITOR-EMBEDDED, RE...

MULTIPLE SUBSTRATE PACKAGE SYSTEMS AND RELATED METHODS