the second connecting process involving a build-up interconnect

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/92224the second connecting process involving a build-up interconnect

Industries

Patents Grantslast 30 patents

Information Patent Grant
Integrating passive devices in package structures
- Patent number 12,132,029
- Issue date Oct 29, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chih-Chia Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level chip scale packaging intermediate structure apparatus a...
- Patent number 12,051,616
- Issue date Jul 30, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package stacking using chip to wafer bonding
- Patent number 11,955,462
- Issue date Apr 9, 2024
- Intel Corporation
- Georg Seidemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with through-mold via
- Patent number 11,869,829
- Issue date Jan 9, 2024
- Amkor Technology Singapore Holding Pte Ltd.
- Dong Joo Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-stacked package-on-package structures
- Patent number 11,664,322
- Issue date May 30, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level chip scale packaging intermediate structure apparatus a...
- Patent number 11,631,611
- Issue date Apr 18, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor package structure
- Patent number 11,469,208
- Issue date Oct 11, 2022
- Taiwan Semiconductor Manufacturing Company Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with multiple coplanar interposers
- Patent number 11,469,210
- Issue date Oct 11, 2022
- Micron Technology, Inc.
- Shing-Yih Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaging methods for semiconductor devices, packaged semiconductor...
- Patent number 11,289,449
- Issue date Mar 29, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chuei-Tang Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Package stacking using chip to wafer bonding
- Patent number 11,239,199
- Issue date Feb 1, 2022
- Intel Corporation
- Georg Seidemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating passive devices in package structures
- Patent number 11,239,205
- Issue date Feb 1, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chih-Chia Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packages including routing dies and methods of formin...
- Patent number 11,177,201
- Issue date Nov 16, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jie Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device that uses bonding layer to join semiconductor...
- Patent number 11,088,131
- Issue date Aug 10, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ming-Fa Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level chip scale packaging intermediate structure apparatus a...
- Patent number 11,037,819
- Issue date Jun 15, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stacked integrated circuit structure and method of forming
- Patent number 10,985,137
- Issue date Apr 20, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip structure and method of forming same
- Patent number 10,971,371
- Issue date Apr 6, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked integrated circuit structure and method of forming
- Patent number 10,964,667
- Issue date Mar 30, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaging method and package structure of wafer-level system-in-pac...
- Patent number 10,930,617
- Issue date Feb 23, 2021
- NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
- Mengbin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaging methods for semiconductor devices, packaged semiconductor...
- Patent number 10,872,878
- Issue date Dec 22, 2020
- Taiwan Semiconductor Manufacturing Company
- Chuei-Tang Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device with through-mold via
- Patent number 10,811,341
- Issue date Oct 20, 2020
- Amkor Technology Singapore Holding Pte Ltd.
- Dong Joo Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level system-in-package structure and electronic apparatus th...
- Patent number 10,811,385
- Issue date Oct 20, 2020
- NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
- Mengbin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package structure and method of manufacturing the same
- Patent number 10,804,244
- Issue date Oct 13, 2020
- Taiwan Semiconductor Manufacturing Company Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-stacked package-on-package structures
- Patent number 10,784,207
- Issue date Sep 22, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device, manufacturing method thereof, and electronic...
- Patent number 10,763,286
- Issue date Sep 1, 2020
- Sony Corporation
- Susumu Hogyoku
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and structures for wafer-level system in package
- Patent number 10,756,056
- Issue date Aug 25, 2020
- NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
- Mengbin Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor device that uses bonding laye...
- Patent number 10,727,217
- Issue date Jul 28, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ming-Fa Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level chip scale packaging intermediate structure apparatus a...
- Patent number 10,672,647
- Issue date Jun 2, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-chip structure and method of forming same
- Patent number 10,665,468
- Issue date May 26, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating passive devices in package structures
- Patent number 10,535,636
- Issue date Jan 14, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chih-Chia Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for the fluidic assembly of micro-LEDs utilizing...
- Patent number 10,535,640
- Issue date Jan 14, 2020
- eLux Inc.
- Jong-Jan Lee
- G02 - OPTICS

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE STACKING USING CHIP TO WAFER BONDING
- Publication number 20240213225
- Publication date Jun 27, 2024
- Intel Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE PERMANENT GLASS ARCHITECTURES FOR STACKED INTEGRAT...
- Publication number 20240113087
- Publication date Apr 4, 2024
- Intel Corporation
- Brandon Marin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Devices and Methods of Manufacture
- Publication number 20220246598
- Publication date Aug 4, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ming-Fa Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked Integrated Circuit Structure and Method of Forming
- Publication number 20220246581
- Publication date Aug 4, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Wei-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device that Uses Bonding Layer to Join Semiconductor...
- Publication number 20210366893
- Publication date Nov 25, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ming-Fa Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked Integrated Circuit Structure and Method of Forming
- Publication number 20210242173
- Publication date Aug 5, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Wei-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Stacked Package-on-Package Structures
- Publication number 20210005556
- Publication date Jan 7, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE
- Publication number 20200411474
- Publication date Dec 31, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- SHIN-PUU JENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Manufacturing Semiconductor Device that Uses Bonding Laye...
- Publication number 20200328200
- Publication date Oct 15, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ming-Fa Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Chip Structure and Method of Forming Same
- Publication number 20200286741
- Publication date Sep 10, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrating Passive Devices in Package Structures
- Publication number 20200152608
- Publication date May 14, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chih-Chia Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20200152603
- Publication date May 14, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- SHIN-PUU JENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Stacked Package-on-Package Structures
- Publication number 20200066643
- Publication date Feb 27, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked Integrated Circuit Structure and Method of Forming
- Publication number 20200035647
- Publication date Jan 30, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Stacked Package-on-Package Structures
- Publication number 20190115300
- Publication date Apr 18, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked Integrated Circuit Structure and Method of Forming
- Publication number 20190115320
- Publication date Apr 18, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei-Ming Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Chip Structure and Method of Forming Same
- Publication number 20190006187
- Publication date Jan 3, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTILEVEL TEMPLATE ASSISTED WAFER BONDING
- Publication number 20180308834
- Publication date Oct 25, 2018
- Skorpios Technologies, Inc.
- Stephen B. Krasulick
- G02 - OPTICS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20180076172
- Publication date Mar 15, 2018
- Amkor Technology, Inc.
- Jong Sik Paek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUMPLESS BUILD-UP LAYER PACKAGE WITH A PRE-STACKED MICROELECTRONIC...
- Publication number 20180047702
- Publication date Feb 15, 2018
- Intel Corporation
- Pramod Malatkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Through Package Via (TPV)
- Publication number 20170040283
- Publication date Feb 9, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
- Publication number 20140374901
- Publication date Dec 25, 2014
- Samsung Electronics Co., Ltd.
- Ma Huishu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fan-Out Package Structure and Methods for Forming the Same
- Publication number 20140346671
- Publication date Nov 27, 2014
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
- Publication number 20140327157
- Publication date Nov 6, 2014
- NOBUO AOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer Level Chip Scale Packaging Intermediate Structure Apparatus a...
- Publication number 20140264933
- Publication date Sep 18, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUMPLESS BUILD-UP LAYER PACKAGE WITH PRE-STACKED MICROELECTRONIC DE...
- Publication number 20140239510
- Publication date Aug 28, 2014
- Pramod Malatkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SUBSTRATE, POWER DISTRIBUTION AND THERMAL SOLUTION FOR DIRECT...
- Publication number 20140225246
- Publication date Aug 14, 2014
- QUALCOMM Incorporated
- Brian Matthew Henderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER DISTRIBUTION AND THERMAL SOLUTION FOR DIRECT STACKED INTEGRAT...
- Publication number 20140225248
- Publication date Aug 14, 2014
- QUALCOMM Incorporated
- Brian M. Henderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BBUL TOP SIDE SUBSTRATE LAYER ENABLING DUAL SIDED SILICON INTERCONN...
- Publication number 20140159250
- Publication date Jun 12, 2014
- Robert M. Nickerson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS
- Publication number 20140138845
- Publication date May 22, 2014
- Deepak V. Kulkarni
- H01 - BASIC ELECTRIC ELEMENTS

the second connecting process involving a build-up interconnect

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Integrating passive devices in package structures

Wafer level chip scale packaging intermediate structure apparatus a...

Package stacking using chip to wafer bonding

Semiconductor device with through-mold via

Multi-stacked package-on-package structures

Wafer level chip scale packaging intermediate structure apparatus a...

Method of manufacturing semiconductor package structure

Semiconductor package with multiple coplanar interposers

Packaging methods for semiconductor devices, packaged semiconductor...

Package stacking using chip to wafer bonding

Integrating passive devices in package structures

Semiconductor packages including routing dies and methods of formin...

Semiconductor device that uses bonding layer to join semiconductor...

Wafer level chip scale packaging intermediate structure apparatus a...

Stacked integrated circuit structure and method of forming

Multi-chip structure and method of forming same

Stacked integrated circuit structure and method of forming

Packaging method and package structure of wafer-level system-in-pac...

Packaging methods for semiconductor devices, packaged semiconductor...

Semiconductor device with through-mold via

Wafer-level system-in-package structure and electronic apparatus th...

Semiconductor package structure and method of manufacturing the same

Multi-stacked package-on-package structures

Semiconductor device, manufacturing method thereof, and electronic...

Methods and structures for wafer-level system in package

Method of manufacturing semiconductor device that uses bonding laye...

Wafer level chip scale packaging intermediate structure apparatus a...

Multi-chip structure and method of forming same

Integrating passive devices in package structures

System and method for the fluidic assembly of micro-LEDs utilizing...

Patents Applicationslast 30 patents

PACKAGE STACKING USING CHIP TO WAFER BONDING

HIGH PERFORMANCE PERMANENT GLASS ARCHITECTURES FOR STACKED INTEGRAT...

Semiconductor Devices and Methods of Manufacture

Stacked Integrated Circuit Structure and Method of Forming

Semiconductor Device that Uses Bonding Layer to Join Semiconductor...

Stacked Integrated Circuit Structure and Method of Forming

Multi-Stacked Package-on-Package Structures

METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE

Method of Manufacturing Semiconductor Device that Uses Bonding Laye...

Multi-Chip Structure and Method of Forming Same

Integrating Passive Devices in Package Structures

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Multi-Stacked Package-on-Package Structures

Stacked Integrated Circuit Structure and Method of Forming

Multi-Stacked Package-on-Package Structures

Stacked Integrated Circuit Structure and Method of Forming

Multi-Chip Structure and Method of Forming Same

MULTILEVEL TEMPLATE ASSISTED WAFER BONDING

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

BUMPLESS BUILD-UP LAYER PACKAGE WITH A PRE-STACKED MICROELECTRONIC...

Through Package Via (TPV)

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Fan-Out Package Structure and Methods for Forming the Same

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Wafer Level Chip Scale Packaging Intermediate Structure Apparatus a...

BUMPLESS BUILD-UP LAYER PACKAGE WITH PRE-STACKED MICROELECTRONIC DE...

DUAL SUBSTRATE, POWER DISTRIBUTION AND THERMAL SOLUTION FOR DIRECT...

POWER DISTRIBUTION AND THERMAL SOLUTION FOR DIRECT STACKED INTEGRAT...

BBUL TOP SIDE SUBSTRATE LAYER ENABLING DUAL SIDED SILICON INTERCONN...

LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS