the second connecting process involving a bump connector

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H01L2224/92133

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

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H01L2224/92133the second connecting process involving a bump connector

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Patents Grantslast 30 patents

Information Patent Grant
Package structure and method of forming the same
- Patent number 12,051,655
- Issue date Jul 30, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jen-Jui Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in package
- Patent number 12,051,667
- Issue date Jul 30, 2024
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in package
- Patent number 11,810,884
- Issue date Nov 7, 2023
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Monolithic chip stacking using a die with double-sided interconnect...
- Patent number 11,784,165
- Issue date Oct 10, 2023
- Intel Corporation
- Anup Pancholi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die package with bridge layer
- Patent number 11,476,125
- Issue date Oct 18, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei Sen Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Monolithic chip stacking using a die with double-sided interconnect...
- Patent number 11,251,158
- Issue date Feb 15, 2022
- Intel Corporation
- Anup Pancholi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in package
- Patent number 11,251,150
- Issue date Feb 15, 2022
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in package
- Patent number 10,861,815
- Issue date Dec 8, 2020
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for making multi-die package with bridge layer
- Patent number 10,643,861
- Issue date May 5, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei Sen Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multichip modules and methods of fabrication
- Patent number 10,490,520
- Issue date Nov 26, 2019
- Invensas Corporation
- Liang Wang
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Logic die and other components embedded in build-up layers
- Patent number 10,453,799
- Issue date Oct 22, 2019
- Intel Corporation
- Deepak V. Kulkarni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in package
- Patent number 10,438,915
- Issue date Oct 8, 2019
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device
- Patent number 10,269,774
- Issue date Apr 23, 2019
- SOCIONEXT INC.
- Takashi Yamada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in package
- Patent number 10,199,346
- Issue date Feb 5, 2019
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multichip modules and methods of fabrication
- Patent number 10,163,833
- Issue date Dec 25, 2018
- Invensas Corporation
- Liang Wang
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Semiconductor package assembly
- Patent number 9,997,498
- Issue date Jun 12, 2018
- Mediatek Inc.
- Tzu-Hung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid interconnect for chip stacking
- Patent number 9,935,081
- Issue date Apr 3, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kuo Lung Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in BBUL package
- Patent number 9,929,119
- Issue date Mar 27, 2018
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package assembly
- Patent number 9,711,488
- Issue date Jul 18, 2017
- Mediatek Inc.
- Tzu-Hung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package assemblies including a glass solder mask...
- Patent number 9,673,131
- Issue date Jun 6, 2017
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die package with bridge layer and method for making the same
- Patent number 9,640,521
- Issue date May 2, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei Sen Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Logic die and other components embedded in build-up layers
- Patent number 9,496,211
- Issue date Nov 15, 2016
- Intel Corporation
- Deepak V. Kulkarni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in BBUL package
- Patent number 9,437,569
- Issue date Sep 6, 2016
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package and method for forming the same
- Patent number 9,379,072
- Issue date Jun 28, 2016
- Xintec Inc.
- Chien-Hung Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bump package and methods of formation thereof
- Patent number 9,373,609
- Issue date Jun 21, 2016
- Infineon Technologies AG
- Meng Tong Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked packaging using reconstituted wafers
- Patent number 9,293,393
- Issue date Mar 22, 2016
- Broadcom Corporation
- Kevin Kunzhong Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assembly tolerant to misplacement of microelectroni...
- Patent number 8,698,323
- Issue date Apr 15, 2014
- Invensas Corporation
- Ilyas Mohammed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with active surface heat remova...
- Patent number 8,421,212
- Issue date Apr 16, 2013
- Stats Chippac Ltd.
- Kang Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level embedded and stacked die power system-in-package packages
- Patent number 8,247,269
- Issue date Aug 21, 2012
- Fairchild Semiconductor Corporation
- Yong Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
- Publication number 20240339428
- Publication date Oct 10, 2024
- Intel Corporation
- Weng Hong TEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
- Publication number 20240332215
- Publication date Oct 3, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jen-Jui Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT...
- Publication number 20240030188
- Publication date Jan 25, 2024
- Intel Corporation
- Anup Pancholi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT...
- Publication number 20230411356
- Publication date Dec 21, 2023
- Intel Corporation
- Anup Pancholi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
- Publication number 20230014450
- Publication date Jan 19, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jen-Jui Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT...
- Publication number 20220093569
- Publication date Mar 24, 2022
- Intel Corporation
- Anup Pancholi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for Making Multi-Die Package With Bridge Layer
- Publication number 20200266074
- Publication date Aug 20, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei Sen Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT...
- Publication number 20200212011
- Publication date Jul 2, 2020
- Intel Corporation
- Anup Pancholi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
- Publication number 20190393180
- Publication date Dec 26, 2019
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTICHIP MODULES AND METHODS OF FABRICATION
- Publication number 20190088607
- Publication date Mar 21, 2019
- Invensas Corporation
- Liang Wang
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
- Publication number 20180145047
- Publication date May 24, 2018
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE ASSEMBLY
- Publication number 20170287877
- Publication date Oct 5, 2017
- MEDIATEK INC.
- Tzu-Hung LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE
- Publication number 20140159228
- Publication date Jun 12, 2014
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED PACKAGING USING RECONSTITUTED WAFERS
- Publication number 20140151900
- Publication date Jun 5, 2014
- BROADCOM CORPORATION
- Kevin Kunzhong Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS
- Publication number 20140138845
- Publication date May 22, 2014
- Deepak V. Kulkarni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bump Package and Methods of Formation Thereof
- Publication number 20140110835
- Publication date Apr 24, 2014
- INFINEON TECHNOLOGIES AG
- Meng Tong Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLY TOLERANT TO MISPLACEMENT OF MICROELECTRONI...
- Publication number 20130334698
- Publication date Dec 19, 2013
- Invensas Corporation
- Ilyas Mohammed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked Packaging Using Reconstituted Wafers
- Publication number 20130154106
- Publication date Jun 20, 2013
- BROADCOM CORPORATION
- Kevin Kunzhong Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL EMBEDDED AND STACKED DIE POWER SYSTEM-IN-PACKAGE PACKAGES
- Publication number 20130001770
- Publication date Jan 3, 2013
- Yong Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ACTIVE SURFACE HEAT REMOVA...
- Publication number 20120068328
- Publication date Mar 22, 2012
- Kang Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL STACKED STRUCTURE AND...
- Publication number 20090115042
- Publication date May 7, 2009
- ZYCUBE CO., LTD.
- Mitsumasa Koyanagi
- H01 - BASIC ELECTRIC ELEMENTS

the second connecting process involving a bump connector

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Package structure and method of forming the same

High density substrate routing in package

High density substrate routing in package

Monolithic chip stacking using a die with double-sided interconnect...

Multi-die package with bridge layer

Monolithic chip stacking using a die with double-sided interconnect...

High density substrate routing in package

High density substrate routing in package

Methods for making multi-die package with bridge layer

Multichip modules and methods of fabrication

Logic die and other components embedded in build-up layers

High density substrate routing in package

Semiconductor device

High density substrate routing in package

Multichip modules and methods of fabrication

Semiconductor package assembly

Hybrid interconnect for chip stacking

High density substrate routing in BBUL package

Semiconductor package assembly

Integrated circuit package assemblies including a glass solder mask...

Multi-die package with bridge layer and method for making the same

Logic die and other components embedded in build-up layers

High density substrate routing in BBUL package

Chip package and method for forming the same

Bump package and methods of formation thereof

Stacked packaging using reconstituted wafers

Microelectronic assembly tolerant to misplacement of microelectroni...

Integrated circuit packaging system with active surface heat remova...

Wafer level embedded and stacked die power system-in-package packages

Patents Applicationslast 30 patents

HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT...

MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT...

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT...

Methods for Making Multi-Die Package With Bridge Layer

MONOLITHIC CHIP STACKING USING A DIE WITH DOUBLE-SIDED INTERCONNECT...

HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE

MULTICHIP MODULES AND METHODS OF FABRICATION

HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE

SEMICONDUCTOR PACKAGE ASSEMBLY

HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE

STACKED PACKAGING USING RECONSTITUTED WAFERS

LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS

Bump Package and Methods of Formation Thereof

MICROELECTRONIC ASSEMBLY TOLERANT TO MISPLACEMENT OF MICROELECTRONI...

Stacked Packaging Using Reconstituted Wafers

WAFER LEVEL EMBEDDED AND STACKED DIE POWER SYSTEM-IN-PACKAGE PACKAGES

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ACTIVE SURFACE HEAT REMOVA...

SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL STACKED STRUCTURE AND...