the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00

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H01L2221/1026the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar

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Patents Grantslast 30 patents

Information Patent Grant
Semiconductor structure and method for forming the same
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Information Patent Grant
Semiconductor device with spacers for self aligned vias
- Patent number 11,984,359
- Issue date May 14, 2024
- Taiwan Semiconductor Manufacturing Company Limited
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Information Patent Grant
Etch damage and ESL free dual damascene metal interconnect
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- Issue date Apr 9, 2024
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
Fully self-aligned via
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Multifunction single via patterning
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Information Patent Grant
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Information Patent Grant
Etch damage and ESL free dual damascene metal interconnect
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Information Patent Grant
Method for fabricating semiconductor device
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Information Patent Grant
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Information Patent Grant
Vias and gaps in semiconductor interconnects
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CHIP package
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Information Patent Grant
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Information Patent Grant
Multifunction single via patterning
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- International Business Machines Corporation
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Information Patent Grant
Methods of producing self-aligned vias
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- Issue date Dec 17, 2019
- Mirocmaterials LLC
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Integrated fan-out package and method for fabricating the same
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Information Patent Grant
Etch damage and ESL free dual damascene metal interconnect
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Etch damage and ESL free dual damascene metal interconnect
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- Chao-Hsun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer structure for high aspect ratio etch
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Metallization method for semiconductor structures
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Self-aligned fine pitch permanent on-chip interconnect structures a...
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- GLOBALFOUNDRIES Inc.
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- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
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SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20230062825
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SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS
- Publication number 20220181207
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- Taiwan Semiconductor Manufacturing Company Limited
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ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
- Publication number 20220059404
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- Taiwan Semiconductor Manufacturing Company, Ltd.
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METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
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INTERCONNECTION STRUCTURE WITH SIDEWALL PROTECTION LAYER
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SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS
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Fully Self-Aligned Via
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- Micromaterials LLC.
- Regina Freed
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CHIP PACKAGE
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- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chen-Hua Yu
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METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
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- Publication date Jun 11, 2020
- SK HYNIX INC.
- Ki-Hong YANG
- H01 - BASIC ELECTRIC ELEMENTS
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MULTIFUNCTION SINGLE VIA PATTERNING
- Publication number 20200126851
- Publication date Apr 23, 2020
- International Business Machines Corporation
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- H01 - BASIC ELECTRIC ELEMENTS
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MULTIFUNCTION SINGLE VIA PATTERNING
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- International Business Machines Corporation
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VIAS AND GAPS IN SEMICONDUCTOR INTERCONNECTS
- Publication number 20200027827
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- Intel Corporation
- Kevin LIN
- H01 - BASIC ELECTRIC ELEMENTS
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CHIP package
- Publication number 20190372000
- Publication date Dec 5, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
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Method For Increasing The Verticality Of Pillars
- Publication number 20190355621
- Publication date Nov 21, 2019
- Micromaterials LLC.
- Christophe Marcadal
- H01 - BASIC ELECTRIC ELEMENTS
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ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
- Publication number 20190279896
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- Taiwan Semiconductor Manufacturing Co., LTD
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SEMICONDUCTOR DEVICE MANUFACTURING METHOD
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- Publication date Mar 29, 2018
- Toshiba Memory Corporation
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MANUFACTURING METHODS TO PROTECT ULK MATERIALS FROM DAMAGE DURING E...
- Publication number 20180061700
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- TOKYO ELECTRON LIMITED
- Xinghua Sun
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ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
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- Publication date Feb 1, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
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Method of Forming Trenches with Different Depths
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- Publication date Jan 25, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chao-Hsun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING TRENCHES WITH DIFFERENT DEPTHS
- Publication number 20170278744
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- Taiwan Semiconductor Manufacturing Co., LTD
- Chao-Hsun Wang
- H01 - BASIC ELECTRIC ELEMENTS
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SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES
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- Publication date Jul 20, 2017
- GLOBALFOUNDRIES INC.
- Chanro Park
- H01 - BASIC ELECTRIC ELEMENTS
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ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
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- Taiwan Semiconductor Manufacturing Co., LTD
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ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
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- Publication date May 1, 2014
- Taiwan Semiconductor Manufacturing Co., LTD
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
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Information Patent Application
SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES A...
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- International Business Machines Corporation
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CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FOR...
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- International Business Machines Corporation
- Veeraraghavan S. Basker
- H01 - BASIC ELECTRIC ELEMENTS

the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor structure and method for forming the same

Semiconductor device with spacers for self aligned vias

Etch damage and ESL free dual damascene metal interconnect

Method for fabricating semiconductor device

Multifunction single via patterning

Self-aligned contact and contact over active gate structures

Fully self-aligned via

Multifunction single via patterning

Semiconductor device with spacers for self aligned vias

Chip package

Etch damage and ESL free dual damascene metal interconnect

Method for fabricating semiconductor device

Method of forming interconnection structure

Vias and gaps in semiconductor interconnects

CHIP package

Curtain airbag device mounting structure and curtain airbag deploym...

Methods of producing self-aligned vias

Methods of producing self-aligned grown via

Multifunction single via patterning

Methods of producing self-aligned vias

Integrated fan-out package and method for fabricating the same

Etch damage and ESL free dual damascene metal interconnect

Manufacturing methods to protect ULK materials from damage during e...

Semiconductor device manufacturing method

Etch damage and ESL free dual damascene metal interconnect

Method of forming trenches with different depths

Multi-layer structure for high aspect ratio etch

Bumpless build-up layer (BBUL) semiconductor package with ultra-thi...

Metallization method for semiconductor structures

Self-aligned fine pitch permanent on-chip interconnect structures a...

Patents Applicationslast 30 patents

SEMICONDUCTOR STRUCTURE

SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

INTERCONNECTION STRUCTURE WITH SIDEWALL PROTECTION LAYER

SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS

Fully Self-Aligned Via

CHIP PACKAGE

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

MULTIFUNCTION SINGLE VIA PATTERNING

MULTIFUNCTION SINGLE VIA PATTERNING

VIAS AND GAPS IN SEMICONDUCTOR INTERCONNECTS

CHIP package

Method For Increasing The Verticality Of Pillars

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

MANUFACTURING METHODS TO PROTECT ULK MATERIALS FROM DAMAGE DURING E...

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

Method of Forming Trenches with Different Depths

METHOD OF FORMING TRENCHES WITH DIFFERENT DEPTHS

SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

BUMPLESS BUILD-UP LAYER (BBUL) SEMICONDUCTOR PACKAGE WITH ULTRA-THI...

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES A...

SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES A...

CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FOR...