the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00

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H01L2221/1026the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar

Industries

Patents Grantslast 30 patents

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Information Patent Grant
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Methods of producing self-aligned vias
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Information Patent Grant
Etch damage and ESL free dual damascene metal interconnect
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- Issue date Jun 4, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sunil Kumar Singh
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Etch damage and ESL free dual damascene metal interconnect
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Etch damage and ESL free dual damascene metal interconnect
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- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS

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ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
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- Micromaterials LLC.
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CHIP PACKAGE
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MULTIFUNCTION SINGLE VIA PATTERNING
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- International Business Machines Corporation
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VIAS AND GAPS IN SEMICONDUCTOR INTERCONNECTS
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- Intel Corporation
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- Micromaterials LLC.
- Christophe Marcadal
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ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
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- Taiwan Semiconductor Manufacturing Co., LTD
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- Toshiba Memory Corporation
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ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
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- Taiwan Semiconductor Manufacturing Co., LTD
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METHOD OF FORMING TRENCHES WITH DIFFERENT DEPTHS
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- Taiwan Semiconductor Manufacturing Co., LTD
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- GLOBALFOUNDRIES INC.
- Chanro Park
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Method for forming a dual damascene structure
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- Taiwan Semiconductor Manufacturing Co., Ltd.
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- Seong-Hee Jeong
- H01 - BASIC ELECTRIC ELEMENTS

the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Etch damage and ESL free dual damascene metal interconnect

Method for fabricating semiconductor device

Multifunction single via patterning

Self-aligned contact and contact over active gate structures

Fully self-aligned via

Multifunction single via patterning

Semiconductor device with spacers for self aligned vias

Chip package

Etch damage and ESL free dual damascene metal interconnect

Method for fabricating semiconductor device

Method of forming interconnection structure

Vias and gaps in semiconductor interconnects

CHIP package

Curtain airbag device mounting structure and curtain airbag deploym...

Methods of producing self-aligned vias

Methods of producing self-aligned grown via

Multifunction single via patterning

Methods of producing self-aligned vias

Integrated fan-out package and method for fabricating the same

Etch damage and ESL free dual damascene metal interconnect

Manufacturing methods to protect ULK materials from damage during e...

Semiconductor device manufacturing method

Etch damage and ESL free dual damascene metal interconnect

Method of forming trenches with different depths

Multi-layer structure for high aspect ratio etch

Bumpless build-up layer (BBUL) semiconductor package with ultra-thi...

Metallization method for semiconductor structures

Self-aligned fine pitch permanent on-chip interconnect structures a...

Self-aligned fine pitch permanent on-chip interconnect structures a...

Etch damage and ESL free dual damascene metal interconnect

Patents Applicationslast 30 patents

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

INTERCONNECTION STRUCTURE WITH SIDEWALL PROTECTION LAYER

SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS

Fully Self-Aligned Via

CHIP PACKAGE

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

MULTIFUNCTION SINGLE VIA PATTERNING

MULTIFUNCTION SINGLE VIA PATTERNING

VIAS AND GAPS IN SEMICONDUCTOR INTERCONNECTS

CHIP package

Method For Increasing The Verticality Of Pillars

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

MANUFACTURING METHODS TO PROTECT ULK MATERIALS FROM DAMAGE DURING E...

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

Method of Forming Trenches with Different Depths

METHOD OF FORMING TRENCHES WITH DIFFERENT DEPTHS

SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

BUMPLESS BUILD-UP LAYER (BBUL) SEMICONDUCTOR PACKAGE WITH ULTRA-THI...

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES A...

SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES A...

CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FOR...

Method for forming a dual damascene structure

METHOD FOR FORMING SEMICONDUCTOR DEVICE