the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00

Current Industry

H01L2221/1026the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar

Industries

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor structure and method for forming the same
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- Issue date Dec 10, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Hwei-Jay Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with spacers for self aligned vias
- Patent number 11,984,359
- Issue date May 14, 2024
- Taiwan Semiconductor Manufacturing Company Limited
- Pokuan Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch damage and ESL free dual damascene metal interconnect
- Patent number 11,955,376
- Issue date Apr 9, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor device
- Patent number 11,817,351
- Issue date Nov 14, 2023
- SK hynix Inc.
- Ki-Hong Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multifunction single via patterning
- Patent number 11,646,222
- Issue date May 9, 2023
- International Business Machines Corporation
- Effendi Leobandung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contact and contact over active gate structures
- Patent number 11,437,273
- Issue date Sep 6, 2022
- Micromaterials LLC
- Yuriy Shusterman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully self-aligned via
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- Issue date Sep 6, 2022
- Micromaterials LLC
- Regina Freed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multifunction single via patterning
- Patent number 11,387,141
- Issue date Jul 12, 2022
- International Business Machines Corporation
- Effendi Leobandung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with spacers for self aligned vias
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- Issue date Mar 1, 2022
- Taiwan Semiconductor Manufacturing Company Limited
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- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package
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- Issue date Nov 16, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch damage and ESL free dual damascene metal interconnect
- Patent number 11,171,041
- Issue date Nov 9, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating semiconductor device
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- Issue date Sep 14, 2021
- SK hynix Inc.
- Ki-Hong Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming interconnection structure
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- Issue date Jul 27, 2021
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- Che-Cheng Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vias and gaps in semiconductor interconnects
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- Intel Corporation
- Kevin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CHIP package
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- Issue date Sep 8, 2020
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- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Curtain airbag device mounting structure and curtain airbag deploym...
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- Toyota Jidosha Kabushiki Kaisha
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Information Patent Grant
Methods of producing self-aligned vias
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- Issue date Mar 24, 2020
- Micromaterials LLC
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of producing self-aligned grown via
- Patent number 10,573,555
- Issue date Feb 25, 2020
- Micromaterials LLC
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multifunction single via patterning
- Patent number 10,559,493
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Effendi Leobandung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of producing self-aligned vias
- Patent number 10,510,602
- Issue date Dec 17, 2019
- Mirocmaterials LLC
- Ying Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated fan-out package and method for fabricating the same
- Patent number 10,431,738
- Issue date Oct 1, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch damage and ESL free dual damascene metal interconnect
- Patent number 10,312,136
- Issue date Jun 4, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing methods to protect ULK materials from damage during e...
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- Issue date May 28, 2019
- Tokyo Electron Limited
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- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device manufacturing method
- Patent number 10,068,796
- Issue date Sep 4, 2018
- TOSHIBA MEMORY CORPORATION
- Toshiyuki Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch damage and ESL free dual damascene metal interconnect
- Patent number 9,786,549
- Issue date Oct 10, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming trenches with different depths
- Patent number 9,779,984
- Issue date Oct 3, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chao-Hsun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer structure for high aspect ratio etch
- Patent number 9,647,022
- Issue date May 9, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tsai-Hao Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bumpless build-up layer (BBUL) semiconductor package with ultra-thi...
- Patent number 9,520,350
- Issue date Dec 13, 2016
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metallization method for semiconductor structures
- Patent number 9,437,488
- Issue date Sep 6, 2016
- Imec VZW
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- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned fine pitch permanent on-chip interconnect structures a...
- Patent number 9,209,126
- Issue date Dec 8, 2015
- GLOBALFOUNDRIES Inc.
- Qinghuang Lin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR STRUCTURE
- Publication number 20240379437
- Publication date Nov 14, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- HWEI-JAY CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS
- Publication number 20240297077
- Publication date Sep 5, 2024
- Taiwan Semiconductor Manufacturing Company Limited
- Pokuan Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20230062825
- Publication date Mar 2, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- HWEI-JAY CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS
- Publication number 20220181207
- Publication date Jun 9, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Pokuan Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
- Publication number 20220059404
- Publication date Feb 24, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
- Publication number 20210375678
- Publication date Dec 2, 2021
- SK HYNIX INC.
- Ki-Hong YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECTION STRUCTURE WITH SIDEWALL PROTECTION LAYER
- Publication number 20210351065
- Publication date Nov 11, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Che-Cheng CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS
- Publication number 20210134672
- Publication date May 6, 2021
- Taiwan Semiconductor Manufacturing Company Limited
- Pokuan Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fully Self-Aligned Via
- Publication number 20210090952
- Publication date Mar 25, 2021
- Micromaterials LLC.
- Regina Freed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE
- Publication number 20200373485
- Publication date Nov 26, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
- Publication number 20200185274
- Publication date Jun 11, 2020
- SK HYNIX INC.
- Ki-Hong YANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIFUNCTION SINGLE VIA PATTERNING
- Publication number 20200126851
- Publication date Apr 23, 2020
- International Business Machines Corporation
- Effendi LEOBANDUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIFUNCTION SINGLE VIA PATTERNING
- Publication number 20200126852
- Publication date Apr 23, 2020
- International Business Machines Corporation
- Effendi LEOBANDUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIAS AND GAPS IN SEMICONDUCTOR INTERCONNECTS
- Publication number 20200027827
- Publication date Jan 23, 2020
- Intel Corporation
- Kevin LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP package
- Publication number 20190372000
- Publication date Dec 5, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method For Increasing The Verticality Of Pillars
- Publication number 20190355621
- Publication date Nov 21, 2019
- Micromaterials LLC.
- Christophe Marcadal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
- Publication number 20190279896
- Publication date Sep 12, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
- Publication number 20180090369
- Publication date Mar 29, 2018
- Toshiba Memory Corporation
- Toshiyuki SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MANUFACTURING METHODS TO PROTECT ULK MATERIALS FROM DAMAGE DURING E...
- Publication number 20180061700
- Publication date Mar 1, 2018
- TOKYO ELECTRON LIMITED
- Xinghua Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
- Publication number 20180033684
- Publication date Feb 1, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming Trenches with Different Depths
- Publication number 20180025938
- Publication date Jan 25, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chao-Hsun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING TRENCHES WITH DIFFERENT DEPTHS
- Publication number 20170278744
- Publication date Sep 28, 2017
- Taiwan Semiconductor Manufacturing Co., LTD
- Chao-Hsun Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES
- Publication number 20170207122
- Publication date Jul 20, 2017
- GLOBALFOUNDRIES INC.
- Chanro Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
- Publication number 20160211174
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- Taiwan Semiconductor Manufacturing Co., LTD
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- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUMPLESS BUILD-UP LAYER (BBUL) SEMICONDUCTOR PACKAGE WITH ULTRA-THI...
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- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
- Publication number 20140117561
- Publication date May 1, 2014
- Taiwan Semiconductor Manufacturing Co., LTD
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT
- Publication number 20130334700
- Publication date Dec 19, 2013
- Taiwan Semiconductor Manufacturing Co., LTD
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES A...
- Publication number 20130032949
- Publication date Feb 7, 2013
- International Business Machines Corporation
- Qinghuang Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES A...
- Publication number 20130032945
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- International Business Machines Corporation
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- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FOR...
- Publication number 20090032491
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- International Business Machines Corporation
- Veeraraghavan S. Basker
- H01 - BASIC ELECTRIC ELEMENTS

the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor structure and method for forming the same

Semiconductor device with spacers for self aligned vias

Etch damage and ESL free dual damascene metal interconnect

Method for fabricating semiconductor device

Multifunction single via patterning

Self-aligned contact and contact over active gate structures

Fully self-aligned via

Multifunction single via patterning

Semiconductor device with spacers for self aligned vias

Chip package

Etch damage and ESL free dual damascene metal interconnect

Method for fabricating semiconductor device

Method of forming interconnection structure

Vias and gaps in semiconductor interconnects

CHIP package

Curtain airbag device mounting structure and curtain airbag deploym...

Methods of producing self-aligned vias

Methods of producing self-aligned grown via

Multifunction single via patterning

Methods of producing self-aligned vias

Integrated fan-out package and method for fabricating the same

Etch damage and ESL free dual damascene metal interconnect

Manufacturing methods to protect ULK materials from damage during e...

Semiconductor device manufacturing method

Etch damage and ESL free dual damascene metal interconnect

Method of forming trenches with different depths

Multi-layer structure for high aspect ratio etch

Bumpless build-up layer (BBUL) semiconductor package with ultra-thi...

Metallization method for semiconductor structures

Self-aligned fine pitch permanent on-chip interconnect structures a...

Patents Applicationslast 30 patents

SEMICONDUCTOR STRUCTURE

SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

INTERCONNECTION STRUCTURE WITH SIDEWALL PROTECTION LAYER

SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS

Fully Self-Aligned Via

CHIP PACKAGE

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

MULTIFUNCTION SINGLE VIA PATTERNING

MULTIFUNCTION SINGLE VIA PATTERNING

VIAS AND GAPS IN SEMICONDUCTOR INTERCONNECTS

CHIP package

Method For Increasing The Verticality Of Pillars

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

MANUFACTURING METHODS TO PROTECT ULK MATERIALS FROM DAMAGE DURING E...

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

Method of Forming Trenches with Different Depths

METHOD OF FORMING TRENCHES WITH DIFFERENT DEPTHS

SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

BUMPLESS BUILD-UP LAYER (BBUL) SEMICONDUCTOR PACKAGE WITH ULTRA-THI...

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

ETCH DAMAGE AND ESL FREE DUAL DAMASCENE METAL INTERCONNECT

SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES A...

SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES A...

CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FOR...