using transistors

Industry

CPC
G11C11/40

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements Storage elements therefor

Current Industry

G11C11/40using transistors

Industries

Patents Grantslast 30 patents

Information Patent Grant
Circuitry borrowing for memory arrays
- Patent number 12,340,832
- Issue date Jun 24, 2025
- Micron Technology, Inc.
- Andrea Martinelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device capable of synchronizing clock signals...
- Patent number 12,340,835
- Issue date Jun 24, 2025
- Samsung Electronics Co., Ltd.
- Seunghwan Hong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recognition system and SRAM cell thereof
- Patent number 12,340,837
- Issue date Jun 24, 2025
- NCKU Research and Development Foundation
- Wei-Li He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scaling out architecture for dram-based processing unit (DPU)
- Patent number 12,340,101
- Issue date Jun 24, 2025
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay control circuit, semiconductor memory device, and delay contr...
- Patent number 12,341,523
- Issue date Jun 24, 2025
- Winbond Electronics Corp.
- Shinya Okuno
- G11 - INFORMATION STORAGE
Information Patent Grant
Refresh control circuit, memory, and refresh control method
- Patent number 12,340,833
- Issue date Jun 24, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Liang Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices having a random number generator for protecting memo...
- Patent number 12,340,834
- Issue date Jun 24, 2025
- NANYA TECHNOLOGY CORPORATION
- Wu-Der Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for performing read protection operation of limiting...
- Patent number 12,340,836
- Issue date Jun 24, 2025
- SK hynix Inc.
- Byung Goo Cho
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method for controlling row hammer
- Patent number 12,334,132
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Ho-Youn Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic address scramble
- Patent number 12,334,138
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Erik T. Barmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and method for controlling row hammer
- Patent number 12,334,130
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Jungmin You
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory devices having adjustable I/O signal line load...
- Patent number 12,334,140
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Seung-Jun Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Write timing compensation
- Patent number 12,334,141
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having merged banks on substrate, and method for oper...
- Patent number 12,334,139
- Issue date Jun 17, 2025
- AP Memory Technology Corporation
- Wenliang Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for determining delay parameter, storage mediu...
- Patent number 12,333,230
- Issue date Jun 17, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Yue Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive wordline refresh
- Patent number 12,334,131
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Yang Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Row hammer refresh operation
- Patent number 12,334,133
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- John Christopher M. Sancon
- G11 - INFORMATION STORAGE
Information Patent Grant
Address refresh check method and apparatus, storage medium, and ele...
- Patent number 12,334,134
- Issue date Jun 17, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Teng Shi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and memory system for performing target refresh opera...
- Patent number 12,334,135
- Issue date Jun 17, 2025
- SK Hynix Inc.
- Chul Moon Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Sacrificial strings in a memory device to detect read disturb
- Patent number 12,334,142
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Quantum circuit optimization using windowed quantum arithmetic
- Patent number 12,333,382
- Issue date Jun 17, 2025
- Google LLC
- Craig Gidney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Independent multi-page read operation enhancement technology
- Patent number 12,334,136
- Issue date Jun 17, 2025
- SK Hynix NAND Product Solutions Corp.
- Naveen Prabhu Vittal Prabhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maximum memory clock estimation procedures
- Patent number 12,334,137
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Erik V. Pohlmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Row access strobe (RAS) clobber and row hammer failure mitigation
- Patent number 12,333,022
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Yang Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit line sense amplifier of semiconductor memory device and semicon...
- Patent number 12,327,584
- Issue date Jun 10, 2025
- Samsung Electronics Co., Ltd.
- Donggeon Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid volatile and non-volatile memory device
- Patent number 12,327,590
- Issue date Jun 10, 2025
- RAMBUS INC.
- Scott C. Best
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller that transmits hammer addresses with different co...
- Patent number 12,327,583
- Issue date Jun 10, 2025
- Samsung Electronics Co., Ltd.
- Sungyong Cho
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical memory architecture including on-chip multi-bank non-v...
- Patent number 12,328,880
- Issue date Jun 10, 2025
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and operating method with mechanism to determine vict...
- Patent number 12,327,582
- Issue date Jun 10, 2025
- Samsung Electronics Co., Ltd.
- Hijung Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for power saving in semiconductor devices
- Patent number 12,327,601
- Issue date Jun 10, 2025
- Yangtze Memory Technologies Co., Ltd.
- Jian Luo
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY, BIT LINE CONTROL METHOD, AND ELECTRONIC DEVICE
- Publication number 20250210098
- Publication date Jun 26, 2025
- CXMT CORPORATION
- Shufang SI
- G11 - INFORMATION STORAGE
Information Patent Application
BACKGROUND DATA REFRESH USING SOFT READS
- Publication number 20250210127
- Publication date Jun 26, 2025
- SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Zion KWOK
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER PERFORMING TRAINING TO IMPROVE COMMUNICATION AND...
- Publication number 20250210079
- Publication date Jun 26, 2025
- SK HYNIX INC.
- Nam Hyeok JEONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CONTROLLING DATA STROBE SIGNALS, AND MEMORY DEVICE USING...
- Publication number 20250210090
- Publication date Jun 26, 2025
- NANYA TECHNOLOGY CORPORATION
- Wu-Der Yang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND ELECTRONIC DEVICE
- Publication number 20250210094
- Publication date Jun 26, 2025
- Semiconductor Energy Laboratory Co., Ltd.
- Shunpei YAMAZAKI
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR CONTROLLING DATA STROBE SIGNALS, AND MEMORY DEVICE USING...
- Publication number 20250210089
- Publication date Jun 26, 2025
- NANYA TECHNOLOGY CORPORATION
- Wu-Der Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus Including Memory Word Line Structure
- Publication number 20250210091
- Publication date Jun 26, 2025
- Micron Technology, Inc.
- Jun Ho Lee
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT DEVICE
- Publication number 20250210092
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- Minho Choi
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING T...
- Publication number 20250210096
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- Kyoungmin Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MICROELECTRONIC DEVICES AND MEMORY DEVICES
- Publication number 20250210101
- Publication date Jun 26, 2025
- Micron Technology, Inc.
- Fatma Arzum Simsek-Ege
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE WITH SHARED BIT LINE SENSE AMPLIFIERS
- Publication number 20250210095
- Publication date Jun 26, 2025
- SAMSUNG ELECTRONICS CO,. LTD.
- Keonhee PARK
- G11 - INFORMATION STORAGE
Information Patent Application
DELAY CONTROL CIRCUIT AND A MEMORY MODULE INCLUDING THE SAME
- Publication number 20250211216
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- Bumsoo LEE
- G11 - INFORMATION STORAGE
Information Patent Application
3D DRAM WITH CMOS-BETWEEN-ARRAY ARCHITECTURE
- Publication number 20250210093
- Publication date Jun 26, 2025
- IMEC vzw
- Hyungrock Oh
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE HAVING CONTROLLABLE BACK GATES AND SHIELDING BIT LINES
- Publication number 20250212394
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- Changyoung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE THREADING WITH STAGGERED DATA TRANSFERS
- Publication number 20250209018
- Publication date Jun 26, 2025
- Rambus Inc.
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM REFRESH
- Publication number 20250210087
- Publication date Jun 26, 2025
- Micron Technology, Inc.
- Gianluca COPPOLA
- G11 - INFORMATION STORAGE
Information Patent Application
POWER MANAGEMENT CIRCUIT AND STORAGE DEVICE
- Publication number 20250210088
- Publication date Jun 26, 2025
- SK HYNIX INC.
- Min Soon HWANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD FOR OPERATING THE SAME
- Publication number 20250210097
- Publication date Jun 26, 2025
- NANYA TECHNOLOGY CORPORATION
- Chien Yu CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC TRANSMITTER CALIBRATION
- Publication number 20250210099
- Publication date Jun 26, 2025
- QUALCOMM Incorporated
- Jaseem AHAMMED
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY STRUCTURE, MANUFACTURING METHOD THEREOF, AND OPERATING METHO...
- Publication number 20250210100
- Publication date Jun 26, 2025
- Macronix International Co., Ltd.
- Feng-Min LEE
- G11 - INFORMATION STORAGE
Information Patent Application
RANDOMIZED REFRESH OPERATIONS
- Publication number 20250201294
- Publication date Jun 19, 2025
- Micron Technology, Inc.
- Michele Scaravilli
- G11 - INFORMATION STORAGE
Information Patent Application
SEPARATED READ BL SCHEME IN 3T DRAM FOR READ SPEED IMPROVEMENT
- Publication number 20250201296
- Publication date Jun 19, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR CONDUCTIVE COUPLING OF BIT LINES USING...
- Publication number 20250201299
- Publication date Jun 19, 2025
- Micron Technology, Inc.
- Jiyun Li
- G11 - INFORMATION STORAGE
Information Patent Application
BOOSTED WRITEBACK VOLTAGE
- Publication number 20250201293
- Publication date Jun 19, 2025
- Rambus Inc.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS
- Publication number 20250201769
- Publication date Jun 19, 2025
- SK HYNIX INC.
- Seong Ju LEE
- G11 - INFORMATION STORAGE
Information Patent Application
CRYOGENIC QUASI-STATIC EMBEDDED DRAM (CQS-eDRAM) FOR ENERGY-EFFICIE...
- Publication number 20250201292
- Publication date Jun 19, 2025
- Shanghaitech University
- Yuhao SHU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROWHAMMER MITIGATION FOR A MEMORY DIE
- Publication number 20250201295
- Publication date Jun 19, 2025
- Rambus Inc.
- Wendy Elsasser
- G11 - INFORMATION STORAGE
Information Patent Application
Sub-Word Line Driver Placement For Memory Device
- Publication number 20250201297
- Publication date Jun 19, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Tzu Chen
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
- Publication number 20250201298
- Publication date Jun 19, 2025
- Samsung Electronics Co., Ltd.
- Sunyoung Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE HAVING DQS COUNTER CIRCUIT
- Publication number 20250191638
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- SHINGO MITSUBORI
- G11 - INFORMATION STORAGE

using transistors

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Circuitry borrowing for memory arrays

Semiconductor memory device capable of synchronizing clock signals...

Recognition system and SRAM cell thereof

Scaling out architecture for dram-based processing unit (DPU)

Delay control circuit, semiconductor memory device, and delay contr...

Refresh control circuit, memory, and refresh control method

Memory devices having a random number generator for protecting memo...

Memory device for performing read protection operation of limiting...

Memory device and method for controlling row hammer

Dynamic address scramble

Memory device and method for controlling row hammer

Semiconductor memory devices having adjustable I/O signal line load...

Write timing compensation

Memory device having merged banks on substrate, and method for oper...

Method and apparatus for determining delay parameter, storage mediu...

Adaptive wordline refresh

Row hammer refresh operation

Address refresh check method and apparatus, storage medium, and ele...

Memory device and memory system for performing target refresh opera...

Sacrificial strings in a memory device to detect read disturb

Quantum circuit optimization using windowed quantum arithmetic

Independent multi-page read operation enhancement technology

Maximum memory clock estimation procedures

Row access strobe (RAS) clobber and row hammer failure mitigation

Bit line sense amplifier of semiconductor memory device and semicon...

Hybrid volatile and non-volatile memory device

Memory controller that transmits hammer addresses with different co...

Hierarchical memory architecture including on-chip multi-bank non-v...

Memory device and operating method with mechanism to determine vict...

Method and apparatus for power saving in semiconductor devices

Patents Applicationslast 30 patents

MEMORY, BIT LINE CONTROL METHOD, AND ELECTRONIC DEVICE

BACKGROUND DATA REFRESH USING SOFT READS

MEMORY CONTROLLER PERFORMING TRAINING TO IMPROVE COMMUNICATION AND...

METHOD FOR CONTROLLING DATA STROBE SIGNALS, AND MEMORY DEVICE USING...

MEMORY DEVICE AND ELECTRONIC DEVICE

METHOD FOR CONTROLLING DATA STROBE SIGNALS, AND MEMORY DEVICE USING...

Apparatus Including Memory Word Line Structure

INTEGRATED CIRCUIT DEVICE

SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING T...

MICROELECTRONIC DEVICES AND MEMORY DEVICES

SEMICONDUCTOR DEVICE WITH SHARED BIT LINE SENSE AMPLIFIERS

DELAY CONTROL CIRCUIT AND A MEMORY MODULE INCLUDING THE SAME

3D DRAM WITH CMOS-BETWEEN-ARRAY ARCHITECTURE

MEMORY DEVICE HAVING CONTROLLABLE BACK GATES AND SHIELDING BIT LINES

MEMORY MODULE THREADING WITH STAGGERED DATA TRANSFERS

MEMORY SYSTEM REFRESH

POWER MANAGEMENT CIRCUIT AND STORAGE DEVICE

MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

DYNAMIC TRANSMITTER CALIBRATION

MEMORY STRUCTURE, MANUFACTURING METHOD THEREOF, AND OPERATING METHO...

RANDOMIZED REFRESH OPERATIONS

SEPARATED READ BL SCHEME IN 3T DRAM FOR READ SPEED IMPROVEMENT

APPARATUSES AND METHODS FOR CONDUCTIVE COUPLING OF BIT LINES USING...

BOOSTED WRITEBACK VOLTAGE

COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS

CRYOGENIC QUASI-STATIC EMBEDDED DRAM (CQS-eDRAM) FOR ENERGY-EFFICIE...

ROWHAMMER MITIGATION FOR A MEMORY DIE

Sub-Word Line Driver Placement For Memory Device

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME

SEMICONDUCTOR DEVICE HAVING DQS COUNTER CIRCUIT