Patent Application
20230034578
Modern Dynamic Random Access Memory (DRAM) and digital Logic circuits are both constructed from semiconductor devices but use different and largely incompatible processes. The high processing temperature and low leakage materials used for DRAM are not mixable with the tiny, high speed and more leaky logic devices. Logic processes continue a path of relentless improvement currently around 15% per year in either speed or reduced power, while DRAM process has a much slower rate of improvement. This means that not only are the processes incompatible, but also the price and performance are drifting out of balance, such that there is a need for new memory devices that can close the gap.
The currently prevalent process for DRAM uses capacitor cells constructed as slim, tall cylinders above the logic for selection and data input and output (I/O). This DRAM process is running into limits due to the need for cylinders large enough for charges to be detected by sense amplifiers after dilution of the charge over the relatively long data-line conductors which connect charge stored in the capacitors to the sense amplifiers which decide if the charge matches a zero or a one. Scaling to smaller device dimensions does not reduce the resistance-capacitance load represented by the data-line, and the cylinder capacitors are nearly at the end of size reduction if they are to retain the charge needed for a 1-transistor, 1-capacitor (1T1C) Dennard memory cell composed in an array with long data-lines which diminish the signal before it reaches sense amplifiers. The fabrication of these cylindrical capacitors is demanding and slow, accounting for much of the cost and production capacity limitation of current DRAM chips.
Various techniques will be described with reference to the drawings, in which:
Systems and methods are descried herein relating to Dynamic Random Access Memory (DRAM) devices. Systems and methods are described herein for dynamic random access memory devices (DRAM). In one aspect, various DRAM cells, formed of layered materials and substantially planar, may be formed in a in vertical orientation, such that the data-lines run perpendicular to the surface of the substrate and any number of layers may be stacked on top of one another. The various stacks of cells may then be arranged in various ways in an area to form a high density of cells, which may be multiples more dense than is currently possible with state of the art DRAM chips. The devices may be conventional capacitor cells with the usual need for refresh, and the other usual features of activation, sensing, write-back, and selection which are common to Dennard-cell 1T1C DRAM. The cells may also use ferroelectric capacitor dielectric thus resulting in devices which hold charge indefinitely without refresh, but in most other respects operate similarly to the conventional cells, while possibly having limitations on the total number of use cycles they can endure. Two example methods of construction with differently proportioned elements and alternative manufacturing steps are detailed.
In some aspect, the new approach described herein abandons cylinder-type capacitors, turns the memory cells on their side with the inevitable smaller capacitance, and frees up some new ways to optimize memory in a 3-dimensional stack of cells. In some aspects, the capacitors become broader structures which can be created with thin, flat layers which may be stacked multiple cells high. The data-lines (also known as bit-lines) become vertical to intersect those multiple thin layers while remaining approximately 20 times shorter than in the 2D surface form. While the thin planar capacitors store less charge than the cylinders, the shorter data-lines function properly with that smaller charge. These flat capacitors are inexpensive due to the simple manufacturing process needed to produce them, and many cell layers can be stacked. This layering technique may be utilized to result in far superior bits per unit area than the current approach, and the simple process to form each layer results in a low cost per bit. The short data-line enables fast operations. The formation uses uniform planes of insulator which are advantageous for advanced dielectrics such as ferroelectrics. The structure also screens cells from their neighbors which reduces disturbance effects. The smaller cell capacitance and short data-lines will allow read and write power to be minimized.
The novel insights that led to the design of the descried memory cell and its variations include one or more of the following 1) to accept the much smaller capacitance but then make it practical with short data-lines in a vertical approach, 2) to accept that the layers of cells will require shaping but to simplify the cell such that the construction costs will be cheap enough per bit to make the whole device worth building even though cell density of a single layer of such primitive devices may not be competitive with the current state of the art for memory cells, and 3) to accept that the processing may require unusual materials or application of uncommon annealing processes.
The heart of each memory cell or device is a planar semiconductor active core, which is formed of material from a uniformly deposited layer, which is then patterned. In some cases, the layers may be annealed to optimize material qualities of semiconductor films ranging from silicon to semiconducting oxides such as TiO2 (titanium dioxide), WO3 (tungsten trioxide), IWO (indium oxide with tungsten doping) or IGZO (indium gallium zinc oxide formulations), or other semiconductors compatible with deposition as thin as a few nanometers, that retain good electrical performance.
The device stacks may have large layer counts leading to high combined capacities, potentially thousands of bits per square micron. This high capacity can amortize the cost of a top or bottom layer of CMOS supporting circuits fabricated in high quality single crystal silicon. When the CMOS layer is bonded on top, an approach used for SOI (silicon on insulator) devices, after the memory layers are formed, allows for annealing processes which may be too hot to be compatible with logic elements. Thus, when the logic layer is added after the annealing there is extra freedom to choose the materials used in the memory cells.
There can also be cost and complexity advantages in having the CMOS support circuits built first and then building the DRAM layers above that logic and analog circuitry. Some materials available, which can be processed at lower temperatures, can form just the same kind of laminar memory structures. In these examples, the materials chosen may be more limited, but this may be outweighed by the advantage of working with a cheaper circuit under memory fabrication. This may provide a lower cost approach avoiding the SOI bonding step, attractive for memory stacks that do not need the ultimate capacity.
The memory device described herein is different from other 3D memory proposals in adhering to the proven single transistor single capacitor (1T-1C) “Dennard cell” principles with speeds and operation which are compatible with existing industry practice. One innovation of the described memory device lies in seeing how that functionality may be maintained while finding a structure that is compatible with extension to multiple layers in the vertical direction, with simple and inexpensive fabrication. Unlike the 3D fabrication of NAND in which potentially hundreds of featureless layers are the key to overall cost reduction, the described DRAM techniques accept that some of the layers will require masking steps to obtain shapes for device elements through etching or selective deposition or implantation, while delivering functionality compatible with prior DRAM devices.
The systems and techniques described herein may enable the production of memory chips or devices which have the functions and capabilities of current DRAM devices but may be manufactured with higher capacity per unit area, at low cost and with good performance. In some aspects, each cell is a 1-transistor 1-capacitor (1T1C) single bit memory based on the principles of the original 1T1C cell which is well known in the industry. The described memory cell may use either an ordinary dielectric, a ferroelectric, or an anti-ferroelectric dielectric in the capacitor. Semiconductor substrates may be constructed where multiple layers of DRAM cells are simply and inexpensively fabricated such that, with many layers, an exceptionally high cell density is obtained which may be coupled with access circuits either below or above the DRAM cells.
Cells with ordinary dielectric will have unlimited endurance and high speed but require refresh as the capacitor charge will leak through the access transistor. Refresh cycles may be reduced or eliminated by operating at lower temperatures which reduce leakage and increase the sub-threshold slope, improving the on/off ratio of the access transistor. Cooler operation may widen the choices for suitable semiconductor thin films within the decks. Even at room temperature, thin film semiconductors such as titanium dioxide with a 100,000,000 to 1 on/off ratio are known and would be suitable to support conventional refresh intervals of 64 milliseconds while supporting access times of a few nanoseconds.
Cells with ferroelectric dielectric will retain charge indefinitely when operated with sufficient positive and negative voltages to reach the necessary hysteresis in the dielectric material. In addition to the persistence of charge they also are tolerant of access channel transistors with less perfect on/off ratios, which provide more choices for semiconductor selection. For example, polysilicon channels with an on/off ratio around 1,000,000 to 1 would be suitable. There may be some limits to the cycles of operation, requiring wear leveling methods to be added to the access path. It will be possible to use the highest performance orthorhombic hafnium-zirconium oxide or other recently discovered ferroelectrics especially if CMOS-after construction is chosen, as will be discussed in greater detail below, since memory stack materials may be used which require annealing without concern for temperature limits in the CMOS devices.
Cells with antiferroelectric dielectric have reported charge retentions of many seconds even at elevated temperature and tolerate moderate access channel performance. They do, however, require different sense amplifiers methods which may require more complex sense amplifiers to be multiplexed for sharing by a broader set of data lines.
The high capacity of the multiple DRAM levels supports the cost of the additional steps needed to integrate CMOS under or over the memory array, since only one final CMOS layer has its cost shared by dozens of memory layers. The resulting devices will enable high capacity, high performance, general purpose memory to be built at low cost per gigabyte and low power of operation compared to current DRAM.
The use of CMOS above has the utility of integrating the densest general-purpose memory— DRAM— alongside the best of logic devices that results in an improvement in performance and reduction in the energy needed for data access. The CMOS layers enable high quality analog and digital circuits to be incorporated with direct access to adjacent memory cells.
Other circuits built at the CMOS level may include the overall interface for the memory chip, error correction, sparing, and other supervisory overhead for the chip. Various forms of interface and control such as Open Memory Interface (OMI), Low Power Double Data Rate (LPDDR), Double Data Rate (DDR), Graphics Double Data Rate (GDDR), or High Bandwidth Memory (HBM), will be feasible. In some aspects, other interfaces and/or controls may be implemented that make better use of the good quality CMOS process for the control and interface logic which offers performance not matched with processes optimized for DRAM elements.
It is also possible to add Processing In Memory (PIM) functionality to the CMOS layer, or to bond one or more additional semiconductor layers on top to implement CMOS functionality which does not compete with the sense amplifiers in the first CMOS layer. This can be facilitated by substrate materials with greater heat conductivity, and in environments which can provide cooler package temperatures.
Non-silicon substrates such as graphite could be used to support the construction of the memory stacks since the memory stacks are not electrically connected to the substrate. Graphite may be toughened by alloying, for example with tungsten or silicon, and offers an order of magnitude better thermal conductivity than silicon. This will support the removal of heat if additional layers of processing logic are bonded or packaged together with the memory stack. Substrates with slightly different thermal expansion coefficients may be accommodated by etching trenches around the memory regions to allow some expansion and contraction.
If silicon is used as the base wafer, it does not need to be highly pure and crystalline, since the memory layers are not electrically connected to the base. It could, for example, be inexpensive epitaxial polysilicon on a carrier plate, or melt-cast polysilicon wafers. Other low-cost silicon sources may be used.
Elements in the memory layers may benefit from annealing and other high temperature processes that improve their semiconductor or dielectric quality. This is especially enabled by a CMOS-last order of construction where the memory stacks may be thermally processed prior to the formation of the CMOS above it, and all the materials in the memory stacks may be selected to be tolerant of the deposition, crystallization, and annealing temperature profiles encountered during the construction of the stacks.
Nevertheless, there are also materials known which can be formed and annealed at temperatures under 400C which are generally compatible with implementations that utilize CMOS-first under the memory, that form devices which would be present during the memory array construction. To allow connections down to the CMOS, below the base conductor level of the memory cells would need to be masked to open a path for vias to be etched downward to start in the CMOS. Both CMOS-first and CMOS-last are compatible with the described 3D DRAM array construction with appropriate choice of materials and matching construction of the vias.
The memory stack and CMOS layers may use different processes but may be integrated in design for a precise match in the position of connecting features. Precise combination and alignment is already used in sequential stacking Silicon on Insulator (SOI) processes which bonds a thin epitaxial blank SOI layer on top and then uses alignment marks in the base, which are visible through such thin epitaxial oxide and silicon, so that the next levels of lithography are aligned within nanometers of the underlying memory stack. The use of these processes allows true 3D integration at the limits of device geometry.
The memory stack does not require power and ground distribution as its devices are passively powered by sense amplifiers and other signal drivers such as the word-line drivers. Areas of the memory substrate which are not used for memory stacks, for example because the CMOS area above must be used for non-memory functions, may be patterned with structures, including capacitors or conductors or inductors, which support power and ground distribution for the CMOS functions.
In some aspects, the multiple, wide ground planes may greatly reduce disturbance effects, and the short data-lines should deliver low latency with small charge transfers. This will support reliable and high-performance operation.
Both volatile and persistent forms are possible, depending on the kind of dielectric in use. The planar construction allows dielectrics of ideal uniformity in thickness and composition to be deposited by a variety of technologies including wet chemical, plasma, sputtering, molecular beam, and vapor deposition schemes, possibly modified by dopant implantation and by annealing. The materials used will each have their ideal deposition methods. The planar construction of the capacitors including fill materials to minimize level changes at the semiconductor edges will minimize material stress from changes in field intensity that occur around folds, generally allowing best results even with complex dielectrics.
In some realizations, the deck may be constructed with two memory facing each other around a central, shared conductor. The upper cell is a mirror image of the lower cell. In that case the use of three ground planes and two semiconductor central electrodes within a deck allows two semiconductor planes with dual-sided capacitors which doubles the capacitance per unit area.
Capacitance per cell will depend upon choice of dielectric and thickness, but values around 1 femtofarad per cell are estimated for conventional capacitor dielectrics with areal density of 100 cells per square micron per deck. This is approximately 10-fold smaller than was found in the cylindrical capacitors for devices in the DDR4 generation. In some aspects, this may be an effective match to data-lines, which may be 20× shorter than for the horizontal data-lines of those same DDR4 devices.
The word-line access vias may utilize unique lithography patterns to give a different access to the word-line for each distinct deck. For example, 24 deck stacks might require 24 different lithography masks specialized just for those word-line layers. The standard approach to providing vias reaching individual layers is the stair-step formation as is found in 3D-NAND chips. In order to avoid too many stair-steps, which takes time to process and space on the chip, there can be a small number, such as 4, of different masks which provide word-line terminations in 4 different places. This allows one stair-step to be divided by 4 (or whatever number is optimum) because there are separate word lines reachable in each stair-step. The small set of different masks would be repeated in groups, so for example 32 decks might be constructed with 4 different word-line masks repeated in a cycle, then 8 stair-steps are etched to allow the word-line vias to reach all 32 word-lines distinctly.
The other way of address the problem of word line implementation is to use mask less lithography, such as electron beam lithography, for just the distinctive details of the layers which need variations in detail. It is not necessary for the entire layer to be drawn with electrons, which would be impractical with current machines. The variations in word lines occupy less than 0.1% of the pattern, so a combination of conventional lithography with a single mask can expose the unchanging parts of the conductor layers which include word-lines, then electron lithography can be applied to finish exposing the resist for just the tiny area needing custom details to extend the word line to a distinct landing. That may be feasible at production rates with currently available multi-beam electron lithography.
Different stages of an example process for creating a layer of a memory cell are described in reference to
The example process may begin with construction of a deck which is a set of layers forming DRAM cells with a central core of semiconductor sandwiched below and above by dielectrics and conductors. The different parts of the semiconductor interact with these other layers to create capacitance, an access channel, and a contact to the data-line. This set of layers for a cell, which will be termed a deck, may then be joined by more layers fabricated one over another to form a stack of multiple decks. In some examples, the active circuitry for sense amplifiers and other system functions may be formed or placed above the multiple decks. In other examples, some or all of the active circuitry may be placed below the first layer of the deck, split between above and below the deck, or placed within the decks.
As described herein, it should be appreciated that some or all layers are deposited by successive methods of vapor, molecular beam, sputtering, liquid chemistry, electroplating, plasma, ion implantation, or other deposition methods used in the semiconductor industry, as may be suitable for fabrication of the specific materials. Etching and removal may be done by evaporation, solvents, acids, reactive plasma, chemically enhanced plasma, and other removal methods used in the semiconductor industry. The methods used for depositing or removing materials at each step may be optimized for construction of a device made of certain materials, as is known by those of ordinary skill in the art.
In processes such as shown in
The sense amplifiers 170 interleave to fill the area above the cell stack and provide connection to every data-line via. The layout is narrow so that it will fit in the same space as a pair of adjacent planar cells from the stack, so the sense amplifiers 170 take up the same area as the underlying cells. Other arrangements are possible, and there are some edge cases which may need dummy data-lines, to serve as references for a first or last bit in a word. In practice, the design and layout of the sense amplifiers may set limits to the length and width of cells. In some cases, it may be beneficial to add data-line isolation transistors to the sense amplifier 170 so that one sense amp may serve a larger memory cell count, which allows the cells to remain small relative to whatever size of sense amplifier is used. It should be appreciated that in various implementations, various numbers of memory ells may be stacked vertically, and the stacks then arranged adjacent to one another in various patterns or arrangements to form a larger memory device of varying sizes and shapes. A grid-like arrangement is illustrated, however other arrangements and patterns are contemplated herein.
Other variations are within the spirit of the present disclosure. Thus, while the disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the invention to the specific form or forms disclosed but, on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the invention, as defined in the appended claims.
The use of the terms “a” and “an” and “the” and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Similarly, use of the term “or” is to be construed to mean “and/or” unless contradicted explicitly or by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to,”) unless otherwise noted. The term “connected,” when unmodified and referring to physical connections, is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. The use of the term “set” (e.g., “a set of items”) or “subset” unless otherwise noted or contradicted by context, is to be construed as a nonempty collection comprising one or more members. Further, unless otherwise noted or contradicted by context, the term “subset” of a corresponding set does not necessarily denote a proper subset of the corresponding set, but the subset and the corresponding set may be equal. The use of the phrase “based on,” unless otherwise explicitly stated or clear from context, means “based at least in part on” and is not limited to “based solely on.”
Conjunctive language, such as phrases of the form “at least one of A, B, and C,” or “at least one of A, B and C,” (i.e., the same phrase with or without the Oxford comma) unless specifically stated otherwise or otherwise clearly contradicted by context, is otherwise understood within the context as used in general to present that an item, term, etc., may be either A or B or C, any nonempty subset of the set of A and B and C, or any set not contradicted by context or otherwise excluded that contains at least one A, at least one B, or at least one C. For instance, in the illustrative example of a set having three members, the conjunctive phrases “at least one of A, B, and C” and “at least one of A, B and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}, and, if not contradicted explicitly or by context, any set having {A}, {B}, and/or {C} as a subset (e.g., sets with multiple “A”). Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of A, at least one of B and at least one of C each to be present. Similarly, phrases such as “at least one of A, B, or C” and “at least one of A, B or C” refer to the same as “at least one of A, B, and C” and “at least one of A, B and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}, unless differing meaning is explicitly stated or clear from context. In addition, unless otherwise noted or contradicted by context, the term “plurality” indicates a state of being plural (e.g., “a plurality of items” indicates multiple items). The number of items in a plurality is at least two but can be more when so indicated either explicitly or by context.
Operations of processes described herein for manufacturing DRAM memory cells of devices can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In an embodiment, a process such as those processes described herein (or variations and/or combinations thereof) for manufacturing one or more DRAM memory devices is performed under the control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof. In an embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In an embodiment, a computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues) within transceivers of transitory signals. In an embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions that, when executed (i.e., as a result of being executed) by one or more processors of a computer system, cause the computer system to perform operations described herein. The set of non-transitory computer-readable storage media, in an embodiment, comprises multiple non-transitory computer-readable storage media, and one or more of individual non-transitory storage media of the multiple non-transitory computer-readable storage media lack all of the code while the multiple non-transitory computer-readable storage media collectively store all of the code. In an embodiment, the executable instructions are executed such that different instructions are executed by different processors—for example, in an embodiment, a non-transitory computer readable storage medium stores instructions and a main CPU executes some of the instructions while a graphics processor unit executes other instructions. In another embodiment, different components of a computer system have separate processors and different processors execute different subsets of the instructions.
Accordingly, in an embodiment, computer systems are configured to implement one or more services that singly or collectively perform operations of processes described herein, and such computer systems are configured with applicable hardware and/or software that enable the performance of the operations. Further, a computer system, in an embodiment of the present disclosure, is a single device and, in another embodiment, is a distributed computer system comprising multiple devices that operate differently such that the distributed computer system performs the operations described herein and such that a single device does not perform all operations.
The use of any and all examples or exemplary language (e.g., “such as”) provided herein is intended merely to better illuminate embodiments of the invention and does not pose a limitation on the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.
Embodiments of this disclosure are described herein, including the best mode known to the inventors for building the described DRAM memory cell. Variations of those embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate, and the inventors intend for embodiments of the present disclosure to be practiced otherwise than as specifically described herein. Accordingly, the scope of the present disclosure includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the scope of the present disclosure unless otherwise indicated herein or otherwise clearly contradicted by context.
All references including publications, patent applications, and patents cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.
In some aspects, the described system and techniques may include one or more of the following features. It should be appreciated that various combinations of these features are completed herein, and that language indicating inclusion of a combination of features is not a requirement that those features operation in combination to provide one or more advantages as described herein.
1. In one aspect, a deck of one-transistor, one-capacitor (1T1C) memory cells are constructed with elements formed from alternating layers of conductor, dielectric insulation, and semiconductor, so that the devices shall be substantially planar and thin, where some of the layers are uniformly deposited and some other layers contain flat shaped elements, where data storage capacitance for the cells shall be formed with one electrode belonging to the device separated by an insulator layer from the other electrode formed of a ground plane which is a substantially horizontal layer within the deck, where the word lines which activate the access gates of each memory cell are incorporated within the planes of the deck, where multiple decks are stacked in alignment above each other, where the data-lines which move the charges to and from the cells are etched and conductor-filled to run vertically through the decks making contacts to the access channels in each deck, where the data-lines terminate with connection either above or below the memory cells which will connect to sense amplifiers, where multiple decks are constructed vertically to obtain multiple layers of memory.
2. The elements of (1) where a filler is added by self-aligned complementary use of the same masks which shaped the device elements, such that the filler shall substantially match the thickness of those other elements, resulting in a substantially level top across both the device elements and the filler.
3. The elements of (1) where the insulating materials used for capacitor or gate dielectrics may be deposited as uniform planar layers between the layers of conductors or semiconductors made substantially planar by use of fillers, such that the insulating layers are of uniform thickness and substantially free of discontinuities such as step changes in the surface level.
4. The elements of (1) where an insulating layer of dielectric may be doped or alloyed in the capacitor areas to optimize for properties including ferroelectric or antiferroelectric behavior.
5. The elements of (1) where multiple decks are accurately aligned to ensure that elements with the same function in each deck are directly above each other and may directly interconnect by vertical vias of width comparable to the smallest elements of the cells.
6. The elements of (5), where at intervals in the process vias are etched through the layers below and filled with suitable conductors completing a vertical circuit which contacts and connects the functionally related elements in multiple layers to form a vertical circuit.
7. The elements of (1) where CMOS sense amps and control elements are added after the memory stack is completed such that prior to CMOS elements being added the memory stack may undergo one or more annealing or other high temperature formation processes which would not be compatible with presence of the CMOS elements.
8. The elements of (1), where when sufficient decks are accumulated that the surface planarity needs to be improved, the process uses a thicker version of one layer which can be planarized to return to an ideal flat surface while preserving the functional sequence of layers in the deck.
9. The elements of (1) where each deck contains substantially the same pattern for the word-line but where the word-line in each deck may be extended to a unique location of contact pad where vias may reach it separately from other word lines above and below, where that unique detail is drawn by use of mask less lithography such as electron beam lithography.
10. The elements of (1), where the semiconductors are formed from silicon which is deposited as a thin film and may be annealed or otherwise treated to refine its properties as an access channel and capacitor electrode.
11. The elements of (1) where the semiconductors are oxides such as titanium dioxide, or tungsten trioxide, or IWO (indium oxide with tungsten doping) or IGZO (indium gallium zinc oxide), which have known properties making them suitable for memory cell access gates.
12. In another aspect, a deck of 1T1C memory cells is constructed such that the deck is substantially planar to allow another deck to be constructed on top, where each deck can be formed of materials deposited and not requiring use of materials which are part of the substrate, where multiples of the cells within each deck are controlled by shared word-lines which isolate the use of any one data-line to just one memory cell in an enabled word, and where the bit cells are connected through access channels to contact vertically etched vias which transfer data values in the form of charge into or out of capacitors formed of a horizontal electrode connected to the access channel and a thin dielectric layer separating a second horizontal ground plane electrode, where multiple decks are constructed vertically to obtain multiple layers of memory.
13. The elements of (12) where multiple decks are constructed aligned exactly above each other such that vertical data-line vias passing through multiple decks shall correctly connect the matching horizontal cell access transistors which controls the flow of charge in or out of the cell's storage capacitor.
14. The elements of (12), where the sense amplifiers and active controls may be formed in a CMOS layer bonded or deposited above the multiple decks of the memory stack and connected to the matching data-line which contacts a vertical set of memory cells.
15. The elements of (14), where high temperature formation and annealing processes may be used prior to the addition of the sense amplifiers and control circuits so that the additive construction of thin films for conductors, semiconductors, and dielectrics may be optimized without the limitations which the presence of analog and switching circuits may require.
16. The elements of (12) where the substrate underlying the memory deck may be of a material such as graphite or ordinary purity silicon or glass, possibly layered or alloyed, materials optimized for low cost, mechanical properties, thermal conductivity, and compatibility with the expansion coefficients of materials used in the memory decks.
17. The elements of (14), where additional analog or switching functions for computation or processing may be included within the CMOS layer beside the sense amplifiers and control circuits or bonded or deposited in one or more additional CMOS layers above.
18. The elements of (12), where the sense amplifiers and active controls may be formed in a CMOS layer below the multiple decks of the memory stack and connected to the matching data-line via which contacts a vertical set of memory cells.
19. The elements of (18), where additional analog or switching functions for computation or processing may be included within the CMOS layer beside the sense amplifiers and control circuits or bonded or deposited in one or more additional CMOS layers above.
