For an integrated circuit (IC) layout designer, there is often a desire to aggregate or densely-pack multiple gate transistors within a certain area of an IC layout while other regions are laid out to have isolated or stand-alone gates. This variation in transistor density within an IC design can influence a transistor's feature size or critical dimension during semiconductor processing. In particular, irregularities of features sizes can become evident during photolithography and those irregularities may be amplified during subsequent deposition or etch processes. In other words, a group of densely-packed transistors may print or etch differently than an isolated transistor, even if they both have common designs within a layout.
The feature size irregularity is due to diffraction and interference effects of light waves as illustrated in
Densely-packed features 114, due to the interference phenomenon from neighbors, will thereby produce an intensity profile with sinusoidal interference fringe pattern 120. Furthermore, the intensity will be at their greatest near the center of the array and taper off toward the edges, with the result that features near the center will print with better fidelity and confidence because they will see more light, while those near the edges will see less light, as illustrated by the intensity profile 120. As an example, assume densely-packed features 114 comprising patterns for five lines. Due to interference fringe pattern from neighboring features and the resulting intensity profile 120, the three lines in the center may be reproduced on the wafer 108 with a more accurate critical dimension than the two outer lines.
As a result of the difference in intensity, isolated 104 and densely-packed 114 features within an IC design will print with different fidelity, resulting in features with different critical dimensions or linewidths. Such a phenomenon is sometimes referred to as the iso-dense bias effect in photolithography. In addition, there may also be uniformity concerns between isolated 104 and densely-packed 114 features across a wafer 108 as the drive towards smaller feature size and larger substrate continues.
Techniques at minimizing the iso-dense bias have included improving the photolithographic processes or utilizing advanced photoresist chemical systems. Other methods include optical corrections with phase-shifting photomasks or off-axis illumination. For further discussion, please refer to a publication by Uzodinma Okoroanyanwu, Materials and Process Issues Delaying the Introduction of ArF into Production, 12 F
Described is a semiconductor device structure with improved fidelity and uniformity and methods of manufacturing thereof. An integrated circuit layout with multiple functional devices such as logic cells and multiplexers having functional patterns are initially defined. Within the layout, at least one layer of non-functional patterns may be physically positioned adjacent to the functional patterns of the at least one layer of functional patterns. The non-functional patterns can take on a plurality of shapes and sizes. Furthermore, at least one layer of filler cells may also be incorporated within the layout adjacent to the functional patterns, whereby the layer of filler cells includes at least one non-functional pattern.
Reference is now made to a conventional functional device 200 as illustrated in
A functional device 200 on a semiconductor wafer may contain various components. These components are constructed of multiple layers of materials in complex patterns depending on device requirements. The layers are produced when complex photomask patterns are reduced onto a semiconductor substrate by photolithographic processes. For example, with a complementary metal oxide semiconductor (CMOS) device, source and drain regions may initially be formed on the substrate, followed by polysilicon gates, aluminum metal lines, passivation layers, and so forth. Additional layers may be repeated or reproduced with different designs to form the desired functional device 200.
Photolithography of a conventional functional device 200 without the presently disclosed embodiments will result in an underlying wafer experiencing maximum intensity beneath the center of the functional pattern 202, with the intensity tapering off toward the edges in a Gaussian bell-shaped intensity distribution profile as previously discussed. Likewise, a conventional functional device 200 with densely-packed functional patterns (not shown) without the presently disclosed embodiments will experience interference phenomenon from neighboring functional patterns. The result is an intensity profile with sinusoidal interference fringe pattern beneath the densely-packed functional patterns (not shown) as previously discussed. Due to this fringe pattern, certain layers of the functional cell 200 may not be as sharp and precisely formed as is desirable.
Additionally, the non-functional patterns 310 may also reduce loading effects during chemical removal processes, such as wet etch, dry etch, or chemical mechanical processing (CMP) near functional patterns 302 on a global wafer level. By balancing adjacent image intensity profiles on a localized level, a functional device 300 will have an overall balance with good image fidelity and uniformity. As more and more functional devices 300 are printed on a substrate, the wafer will have optimized loading effects because any imbalance has been minimized by the addition of non-functional patterns 310 adjacent to functional patterns 302, thereby allowing both patterns 310, 302 to experience favorable chemical removal processes. The non-functional patterns 310 balance feature densities on a microscopic or localized level, as well as an overall greater balance on a macroscopic or global wafer level, thereby producing functional devices 300 with generally better critical dimension control and wafers with optimal surface planarization.
In one embodiment, the non-functional patterns 310 may be a metal, a semiconductor, or a combination thereof. In another embodiment, the layer of non-functional pattern 310 may be a metal layer, a polysilicon layer, a semiconductor layer, or a combination layer thereof. In yet another embodiment, the non-functional pattern 310 may be formed of a semiconductor substrate. The resulting material formed on the functional device by the non-functional patterns 310 will be driven by material used for the functional patterns 302 of the layer of interest. In addition, although the non-functional pattern 310 as illustrated is rectangular in shape, it can take on any polygonal shape such as a triangle, a square, a parallelogram, a diamond, or a trapezoid. Furthermore, the non-functional pattern 310 may also be in the shape of a plane curve such as a circle, an ellipse, a line, a parabola, or a hyperbola.
There are certain requirements that these non-functional features 310 may be designed to satisfy. In one embodiment, the total area of the non-functional patterns 310 may be designed to be substantially the same as the total area of the functional patterns 302. In another embodiment, the total area of the non-functional patterns 310 may be designed to be substantially less than about 80% of the total area of the functional device 300. The total area of the functional device 300 includes functional patterns 302 as well as non-functional patterns 310. Furthermore, the total area of the functional device 300 may also include any and all remaining active or passive elements within the functional device 300. In still another embodiment, a pattern density of about 10% to 60% is preferred when adding functional patterns 302 and/or non-functional patterns 310 to the functional device 300. The pattern density is defined as the total area of the layers (including functional patterns 302 and non-functional patterns 310) divided by the total area of the functional device 300.
As illustrated, the non-functional patterns 310 have a certain minimum width 312 similar to that of the minimum width 308 of the functional pattern 302. In one embodiment, the spacing 314 between the functional pattern 302 and the non-functional pattern 310 may be designed to be substantially at least half of the minimum width 308 of the functional pattern 302. In another embodiment, the spacing 314 between the functional pattern 302 and the non-functional pattern 310 may be designed to be substantially no greater than one and one-half times or 150% of the minimum geometric dimension 316 of the functional device 300. More specifically, the spacing 314 may be designed to be substantially no greater than 85% of the minimum geometric dimension 316.
In another embodiment, at least a layer of filler cells 400 containing one or more non-functional patterns 402 may be used within an IC layout design.
Taking the layout in
Looking now at the bottom row of
The benefits of the presently disclosed embodiments not only minimize the iso-dense bias effect, they also improve feature size fidelity and uniformity across a wafer. Although there are certain design requirements to follow for utilizing the presently disclosed embodiments, the basic design rules still have to be followed. In other words, an IC layout designer should not break the fundamental design rules simply because of his or her desire to use the presently disclosed embodiments. Furthermore, the presently disclosed embodiments may also save layout space because isolated devices may now be placed closer to each other without any layout rule constraints or photolithographic iso-dense bias concerns.
It will be appreciated by those of ordinary skill in the art that the invention can be embodied in other specific forms without departing from the spirit or essential character thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes that come within the meaning and ranges of equivalents thereof are intended to be embraced therein.
Additionally, the section headings herein are provided for consistency with the suggestions under 37 C.F.R. §1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the invention(s) set out in any claims that may issue from this disclosure. Specifically, a description of a technology in the “Background” is not to be construed as an admission that technology is prior art to any invention(s) in this disclosure. Neither is the “Summary” to be considered as a characterization of the invention(s) set forth in the claims found herein. Furthermore, any reference in this disclosure to “invention” in the singular should not be used to argue that there is only a single point of novelty claimed in this disclosure. Multiple inventions may be set forth according to the limitations of the multiple claims associated with this disclosure, and the claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of the claims shall be considered on their own merits in light of the specification, but should not be constrained by the headings set forth herein.