The present disclosure relates generally to memory devices, and more particularly to bank access methods for memory devices.
Memory devices, such as quad data rate static random access memories (SRAMs) can latch address values on both rising and falling edges of a timing clock for high speed, high throughput operations.
Referring to
Referring still to
At time t3, another read command can be received on the next rising edge of CK. At time t4, the corresponding bank (BankC) can be accessed for the read operation.
At time t5, another write command can be received.
At time t6, a write operation in BankB can be performed in response to the bank address latched at time t2.
It is noted that in operations performed at the access speeds shown in
Referring to
Similarly, at time t5, the read operation to BankE (corresponding to BNKE latched at time t4) overlaps the write operation to BankB (corresponding to BNKB latched at time t1, in a previous cycle). At time at time t7, the read operation to BankG (corresponding to BNKG latched at time t6) overlaps the write operation to BankD (corresponding to BNKD latched at time t3, in a previous cycle).
To ensure proper operations, restrictions are placed on bank addresses so that the same bank is not subject to the overlapping read and write operations. Accordingly, as shown in
Conventionally, to ensure such bank restrictions are maintained, a memory device can compare a read bank address (received on a rising edge of CK) to write bank addresses received in a previous clock cycle.
To ensure sufficient time is provided for comparing addresses, a “no operation” (NOP) cycle is inserted between times t2 and t3. It is understood that the access to BankF is delayed due to the insertion of the NOP cycle until time t7.
At time t4, following the NOP cycle, a read operation can be to any bank, as there is no possible overlapping write operation. Following time t4, read and write operations can continue as described, but with restrictions being based on the new write bank (BankF) received at time t1.
Accordingly, in response to a read operation at time t6, the corresponding BankD can be accessed for a read operation, but such a bank must be different from BankF, being accessed in response to the new write bank received at time t1.
Various embodiments will now be described that include memory devices that enable accesses to multiple banks in response to more than one address received in a same clock cycle. Unlike conventional memory devices, bank accesses can be considerably less restrictive, only requiring accesses within a same cycle being limited to different banks. Banks accessed in previous cycles are not considered.
Referring to
At time t1, in the same clock cycle, a second command can be received for an address on another bank (BNKB) on a falling edge of CK. An address received on a falling edge can be compared to that received on the rising edge of the same clock cycle. That is, in order for the operation to be valid, BNKB must correspond to a bank different from that of BNKA.
At time t2, after the falling edge of CK, and in response to the addresses received at both times t0 and t1 (i.e., in the same clock cycle), the corresponding banks (BankA and BankB) can be accessed in parallel. This is in contrast to a conventional operation, like that of
At time t3, in the next clock cycle, another command can be received on the rising edge of CK directed to address in a bank (BNKx). However, in sharp contrast to conventional operations, there are no bank restrictions on such an access. That is, BNKx can be any bank of the memory device.
It is noted that in some embodiments, a type of access can be restricted according to clock transition type. In a very particular embodiment, read commands can be restricted to rising edges of CK, while write commands are restricted to falling edges of CK. However, in other embodiments any combination of operations can be accommodated on rising and falling clock transitions of a same cycle (e.g., read-read, read-write, write-read, write-write).
In the embodiment of
A bank access circuit 408 can provide the limited bank address comparison as described for embodiments herein. In some embodiments, bank access circuit 408 can limit accesses to banks (406) by comparing bank addresses received in the same clock cycle, and not with regard to any address received in a previous clock cycle. In a very particular embodiment, bank access circuit 408 can compare a bank address received on the falling edge of a clock cycle to any address received on the rising edge of the same cycle.
I/O connections 410 can provide connections to receive address signals and data signals, including inputs for write data and outputs for read data. In some embodiments, such connections can present a separated bus with separate inputs for write data (D) as compared to outputs for read data (Q). However, in other embodiments, one or more data buses can provide paths for read and write data (DQ buses).
As shown, various combinations of bank addresses (Bx, By) for various combinations of operations (R, W) can be received by the memory device. Unlike conventional approaches, like that of
It is understood that in the very particular example of operations shown in
While embodiments above have shown methods and devices that access two banks per cycle, alternate embodiments can access more than two banks per cycle. One such embodiment is shown in
Referring to
In some embodiments, a memory device having bank access operations as described herein, can operate with a latency. For example, read data can be output following a read latency (e.g., 8 cycles) after the reception of a read command. In addition, write data can be written into a memory bank after write-to-array latency (e.g., 13 clock cycles) following the initial storing (e.g., latching) of such write data. In such embodiments, write data and corresponding write addresses can be stored prior to write data being actually written into memory cells of the device.
To ensure data coherency, a memory device can include a late write circuit that enables such stored write data to be output in response to read addresses. One such embodiment is shown in
A CAM block 616 can store address values for write data that is subsequently stored in memory banks of the device (i.e., is subject to a write-to-array latency). A CAM block 616 can compare a received read address to such stored write addresses to see if the read operation is intended for a location subject to a future write operation. A write data store 618 can store write data accessible by data output from a CAM block 616. A write data path 620 can include write data latches and other suitable circuits (e.g., write amplifiers, etc.) for inputting write data to the device.
In response to a read command and address, the read address (RADD) can be applied to read path 614. Such an operation can result in read data being output from a memory bank.
In addition, the read address (RADD) can also be applied to CAM block 616, where it can be compared to stored write addresses, substantially simultaneously. If a read address matches a stored write address, the matching address (madd) can be forwarded to write data store 618 and a match indication (match) can be activated. A match indication (match) can control a MUX 622.
Accordingly, if a read address does not match a write address stored in CAM block 616, a read data value from read path 614 can be output via MUX 622. However, if a read address matches a write address stored in CAM block 616, a write value from write data store 618 can be output via MUX 622 instead of that from a memory bank.
Referring to
Memory blocks 706 can be accessed according to unique block addresses, which in some embodiments can be selected bits of a received address. Address decoder 726 can decode read and write addresses to access storage locations for read and write data (Q and D). In a particular embodiment, memory blocks 706 can have a dual port architecture, enabling simultaneous read and write accesses.
Address register 702 can store addresses received during single clock cycles as described herein, or an equivalent. Address comparator 704 can compare bank addresses received in a same clock cycle. In one particular embodiment, address comparator 704 can compare a bank address latched on a falling edge of a clock signal CK to that latched on the rising edge of the same clock cycle.
CAM block 716, write data store 718 and MUX 722 can operate as described for
Clock generator circuit 728 can generate internal clock signals that are in synchronism with, but not necessarily phase aligned to, an input clock (CK). Such internal clock signals can include, but are not limited to, signals for latching address values (ADD), and latching data values in a double data rate (DDR) fashion, including a write data clock DK and read data clock CQ. Read data can be output in response to rising and falling edges of read data clock CQ, and write data can be latched on rising and falling edges of write data clock DK.
Control logic 730 can receive command data and determine when particular operations are to be executed by the memory device 700, including read and write operations. In response to such commands, control logic 730 can generate control signals (CTRL) for controlling various sections of the memory device 700.
It is understood that control logic 730 can include any of various interfaces. For example, in some embodiments, control logic 730 can have a synchronous SRAM interface. However, in alternate embodiments, control logic 730 can have a dynamic RAM (DRAM) type interface, latching bifurcated addresses (e.g., row addresses and column addresses) in response to particular control signals (e.g., /RAS, /CAS signals).
In addition or alternatively, while
While the above embodiments have shown various devices, circuits and methods, additional methods will now be described with reference to flow diagrams.
A method 800 can also include preventing an access operation in response to the comparison of bank addresses of the same cycle and not in response to any bank address stored in a previous cycle 856. Such an action is in sharp contrast to conventional approaches that compare a bank address received in one cycle to those received in a previous cycle.
It should be appreciated that in the foregoing description of exemplary embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element.
Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.
This application is a continuation of U.S. patent application Ser. No. 13/727,505, filed Dec. 26, 2012, now U.S. Pat. No. 8,705,310, issued Apr. 22, 2014, which claims priority to U.S. Provisional Patent Application No. 61/693,090 filed on Aug. 24, 2012, all of which are incorporated by reference herein in their entirety.
Number | Name | Date | Kind |
---|---|---|---|
4796232 | House | Jan 1989 | A |
4887240 | Garverick et al. | Dec 1989 | A |
5831906 | Yih et al. | Nov 1998 | A |
5875470 | Dreibelbis et al. | Feb 1999 | A |
5991230 | Urakawa | Nov 1999 | A |
6166946 | Naffziger | Dec 2000 | A |
6205523 | Joffe et al. | Mar 2001 | B1 |
6272067 | Sun et al. | Aug 2001 | B1 |
6314047 | Keay et al. | Nov 2001 | B1 |
6324104 | Matsui | Nov 2001 | B1 |
6381684 | Hronik et al. | Apr 2002 | B1 |
6489819 | Kono et al. | Dec 2002 | B1 |
6584036 | Kurjanowicz et al. | Jun 2003 | B2 |
6600693 | Kim | Jul 2003 | B2 |
6745277 | Lee et al. | Jun 2004 | B1 |
6967861 | Braceras et al. | Nov 2005 | B2 |
7142477 | Tran et al. | Nov 2006 | B1 |
7327597 | Wong | Feb 2008 | B1 |
7653780 | Takahashi | Jan 2010 | B2 |
7990973 | Hao et al. | Aug 2011 | B2 |
8149643 | Tzou et al. | Apr 2012 | B2 |
8705310 | Tran et al. | Apr 2014 | B2 |
20010017792 | Takahashi et al. | Aug 2001 | A1 |
20040240288 | Takahashi | Dec 2004 | A1 |
20050210215 | Sezaki et al. | Sep 2005 | A1 |
20060193160 | Hanzawa et al. | Aug 2006 | A1 |
20060292292 | Brightman et al. | Dec 2006 | A1 |
20080133809 | Saito et al. | Jun 2008 | A1 |
20090282316 | Lingam et al. | Nov 2009 | A1 |
20090323454 | Noh | Dec 2009 | A1 |
20100103762 | Tzou et al. | Apr 2010 | A1 |
20110058421 | Warren | Mar 2011 | A1 |
20120008378 | Maheshwari | Jan 2012 | A1 |
20120243301 | Maheshwari et al. | Sep 2012 | A1 |
20140340978 | Tran et al. | Nov 2014 | A1 |
Number | Date | Country |
---|---|---|
2009059452 | Mar 2009 | JP |
Entry |
---|
Altera Corporation, QDR SRAM Controller Function, Application Note 133, ver 1.0, Dec. 2000. |
Altera Corporation, “QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices”, Application Note 349, ver 1.0, May 2004. |
U.S. Appl. No. 13/727,505: “Access Methods and Circuits for Memory Devices Having Multiple Banks” Thinh Tran et al., filed on Dec. 26, 2012; 27 pages. |
English machine translation of JP2009095452 taken from Internet:http://worldwide.espacenet.com. |
Interfacing Xilinx Spartan-II FPGA,http://www.datasheets.org.uk/CY7C1302—CY7C1304/Datasheet-09/DSA00154448.html; 3 pages. |
USPTO Advisory Action for U.S. Appl. No. 13/727,505 dated Aug. 26, 2013; 3 pages. |
USPTO Final-Rejection for U.S. Appl. No. 13/727,505 dated Jul. 10, 2013; 15 pages. |
USPTO Non Final Rejection for U.S. Appl. No. 13/727,505 dated Oct. 24, 2013; 12 pages. |
USPTO Non-Final Rejection for U.S. Appl. No. 13/727,505 dated Mar. 15, 2013; 24 pages. |
USPTO Notice of Allowance for U.S. Appl. No. 13/727,505 dated Feb. 6, 2014; 8 pages. |
White Electronics Design Corporation,“SSRAM Overview Application Note”, Oct. 2001. 6 pages. |
International Search Report for International Application No. PCT/US2011/043481 dated Jan. 2, 2012; 3 pages. |
USPTO Advisory Action for U.S. Appl. No. 13/179,307 dated Oct. 24, 2013; 2 pages. |
USPTO Advisory Action for U.S. Appl. No. 13/179,307 dated Nov. 23, 2015; 3 pages. |
USPTO Final Rejection for U.S. Appl. No. 13/179,307 dated Aug. 21, 2013; 32 pages. |
USPTO Final Rejection for U.S. Appl. No. 13/179,307 dated Sep. 11, 2015; 20 pages. |
USPTO Final Rejection for U.S. Appl. No. 13/179,307 dated Dec. 19, 2014; 20 pages. |
USPTO Non-Final Rejection for U.S. Appl. No. 13/179,307 dated Feb. 19, 2013; 16 pages. |
USPTO Non-Final Rejection for U.S. Appl. No. 13/179,307 dated Jun. 18, 2015; 19 pages. |
USPTO Non-Final Rejection for U.S. Appl. No. 13/179,307 dated Jul. 29, 2014; 18 pages. |
Written Opinion of the International Searching Authority for International Application No. PCT/US2011/043481 mailed Jan. 2, 2012; 4 pages. |
U.S. Appl. No. 14/866,260: “Access Methods and Circuits for Memory Devices Having Multiple Channels and Multiple Banks,” Jun Li et al., filed on Sep. 25, 2015; 38 pages. |
SIPO Office Action for Application No. 201110263752.3 dated May 10, 2016; 6 pages. |
USPTO Non-Final Rejection for U.S. Appl. No. 13/179,307 dated Mar. 11, 2016; 18 pages. |
USPTO Notice of Allowance for U.S. Appl. No. 14/866,260 dated Feb. 4, 2016; 9 pages. |
USPTO Notice of Allowance for U.S. Appl. No. 13/179,307 dated Jul. 1, 2016; 7 pages. |
USPTO Notice of Allowance for U.S. Appl. No. 13/179,307 dated Oct. 6, 2016; 5 pages. |
USPTO Notice of Allowance for U.S. Appl. No. 14/866,260 dated Jun. 2, 2016; 10 pages. |
USPTO Notice of Allowance for U.S. Appl. No. 14/866,260 dated Sep. 14, 2016; 10 pages. |
USPTO Notice of Allowance for U.S. Appl. No. 14/866,260 dated Jan. 5, 2017; 9 pages. |
Number | Date | Country | |
---|---|---|---|
20140340978 A1 | Nov 2014 | US |
Number | Date | Country | |
---|---|---|---|
61693090 | Aug 2012 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 13727505 | Dec 2012 | US |
Child | 14258950 | US |