Patent Application
20170084346
This application relates to the operation of re-programmable nonvolatile memory such as semiconductor flash memory, resistive memory, phase change memory, and the like.
Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, and retains its stored data even after power is turned off. Also, unlike ROM (read only memory), flash memory is rewritable similar to a disk storage device.
Flash EEPROM is similar to EEPROM (electrically erasable and programmable read-only memory) in that it is a non-volatile memory that can be erased and have new data written or “programmed” into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) to be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions. Flash memory such as Flash EEPROM allows entire blocks of memory cells to be erased at the same time.
The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
Nonvolatile memory devices are also manufactured from memory cells with a dielectric layer for storing, or “trapping” charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
Many nonvolatile memories are formed along a surface of a substrate (e.g. silicon substrate) as two dimensional (2D), or planar, memories. Other nonvolatile memories are three dimensional (3-D) memories that are monolithically formed in one or more physical levels of memory cells having active areas disposed above a substrate.
In a three dimensional memory system, blocks may be formed by separately-selectable portions. For example, in a NAND flash memory, a set of strings may share select lines so that such a set of strings in a block is separately-selectable. In other memories, other arrangements may result in separately-selectable portions that may have characteristics that can be measured and used to identify when to adjust operating parameters such as programming voltage for the respective portions. In resistive memories (e.g. ReRAM) local bit lines may extend vertically with word lines extending horizontally and resistive memory elements extending between local bit lines and word lines at different levels. A row of such local bit lines may be selected together by a row select line. A similar arrangement may be used for other memory elements such as phase change memory. An alternative arrangement, which may be referred to as “cross-point memory” includes word lines and bit lines extending horizontally at different heights above a substrate surface and in different directions (e.g. orthogonal) with memory elements extending vertically between word lines and bit lines. Memory elements may be resistive elements, charge storage or trapping elements, phase change elements, or any other suitable memory elements.
A block in a three-dimensional nonvolatile memory may include multiple separately-selectable sets of NAND strings some of which may have characteristics that are outside the normal range of characteristics for NAND strings, which may cause them to fail at some point, either during testing or during operation. For example, an erase fail may occur because current flow through a separately-selectable set of NAND strings during erase-verify is low as a result of a resistance in series with erased memory cells. Such a resistance may be, for example, due to a poor connection between the NAND string and a bit line, or between the NAND string and a common source, or may be due to one or more select transistors, or some other element. Low current due to such a resistance may be overcome by applying a higher bit line voltage. This can be done on a string by string basis, column by column basis (where a column includes multiple bit lines), or for a whole separately-selectable set of NAND strings. A record may be maintained to indicate bit line voltages to use. Low current caused by select transistors may be brought to an acceptable level by applying increased select line voltage. Data stored in portions of a block that require modified parameters such as increased bit line or select line voltages may be stored with an increased redundancy ratio to ensure that data is safely maintained.
An example of a three dimensional nonvolatile memory system includes: a three dimensional nonvolatile memory block that contains a plurality of separately-selectable portions, an individual separately-selectable portion containing a plurality of bit lines extending perpendicular to a substrate surface; a sensing unit configured to sense bit line current and/or voltage for bit lines of the plurality of separately-selectable portions of the block and to compare respective results of the sensing for individual separately-selectable portions with a reference; and an adjustment unit that is in communication with the sensing unit, the adjustment unit configured to individually modify operating parameters for one or more of the plurality of separately-selectable portions of the block in response to the comparing of respective results for the one or more of the plurality of separately-selectable portions of the block with the reference.
The three dimensional nonvolatile memory block and the sensing unit may be located in a memory die and the adjustment unit may be located in a controller die. A plurality of global bit lines may extend parallel to the substrate surface in a first direction and the plurality of bit lines may be connected to the plurality of global bit lines by a plurality of select transistors. A select line may extend parallel to the substrate surface in a second direction that is orthogonal to the first direction, the select line coupled to the plurality of select transistors to separately-select the plurality of bit lines. An individual bit line may extend through a plurality of word line levels and may form an individual memory element at each of the plurality of word line levels. The memory element may be a charge storage or charge trapping element, a resistive element, or a phase change memory element. The adjustment unit may be configured to individually modify programming voltage and/or select voltage for each of the plurality of separately selectable portions in response to the comparing. A temperature input may be provided to the adjustment unit, and the adjustment unit may be further configured to modify operating parameters in response to the temperature input.
An example of a three dimensional nonvolatile memory includes: a plurality of first lines extending along a first direction at a first height above a substrate surface; a plurality of second lines extending along a second direction at a second height above the substrate surface, the second direction being orthogonal to the first direction; a plurality of memory elements, an individual memory element extending from a first line at the first height to a second line at the second height; a sensing unit that is configured to sense current and/or voltage of the first line and to compare results of the sensing with a reference; and an adjustment unit that is in communication with the sensing unit, the adjustment unit configured to modify operating parameters for memory elements connected to the first line in response to the comparison.
The adjustment unit may be configured to modify programming voltage for memory elements connected to the first line in response to the comparison. The adjustment unit may be configured to modify read voltage for memory elements connected to the first line in response to the comparison. The plurality of memory elements may be resistive memory elements, phase change memory elements, or charge storage elements. Additional first lines may extend in the first direction at additional heights above the substrate surface, additional second lines may extend in the second direction at additional heights above the substrate surface, and additional memory elements may extend from additional first lines to additional second lines, and the adjustment unit may be configured to modify operating parameters for memory elements located at a plurality of different heights above the substrate surface according to their respective heights. A temperature input may be provided to the adjustment unit, and the adjustment unit may be further configured to modify operating parameters in response to the temperature input. The plurality of first lines, the plurality of second lines, the plurality of memory elements, and the sensing unit may be located in a first die and the adjustment unit may be located in a second die, the input to the adjustment unit generated by a temperature sensor in the second die.
An example of a method of operating a three dimensional nonvolatile memory that includes multiple separately-selectable portions in a block, includes: measuring electrical current through a conductive line in a separately-selectable portion; comparing the electrical current with predetermined criteria; if the current does not meet the predetermined criteria then calculating one or more voltage offsets; and subsequently, adjusting voltages applied to lines in the separately-selectable portion by the one or more voltage offsets when accessing memory elements in the separately-selectable portion while other voltages applied to other separately-selectable portions of the block remain unadjusted when accessing the other separately-selectable portions of the block.
The one or more voltage offsets for the separately-selectable portion may be recorded in a table and subsequently the one or more voltage offsets may be obtained from the table prior to accessing the separately selectable portion. An enhanced redundancy scheme may be applied to data stored in separately-selectable portions that do not meet the predetermined criteria, the enhanced redundancy scheme providing a higher degree of error correction capacity than a regular redundancy scheme that is applied to data stored in sets of strings that meet the predetermined criteria. The temperature of the three dimensional nonvolatile memory may be measured and voltages applied to lines in the separately-selectable portion and in other separately-selectable portions may be adjusted according to the temperature measured.
An example of a three dimensional nonvolatile memory system includes: a block that contains a plurality of separately-selectable sets of NAND strings; a bit line current sensing unit that is configured to sense bit line current for a separately-selectable set of NAND strings of the block and to compare the bit line current to a minimum current; and a bit line voltage adjustment unit that is in communication with the bit line current sensing unit, the bit line voltage adjustment unit configured to apply a first bit line voltage to separately-selectable sets of NAND strings that have bit line currents greater than the minimum current, and configured to apply a second bit line voltage to separately-selectable sets of NAND strings that have bit line currents less than the minimum current, the second bit line voltage being greater than the first bit line voltage.
The first and second bit line voltages may be applied during programming, reading, or erasing of the block. The bit line current sensing unit may be configured to sense bit line current for each of the plurality of separately-selectable sets of NAND strings of the block and to compare each of the bit line currents with the minimum current, and the bit line voltage adjustment unit may be configured to apply at least the second bit line voltage to any of the plurality of separately-selectable sets of NAND strings in the block that have bit line currents that are less than the minimum current. A table may record an entry for each separately-selectable set of NAND strings that receives at least the second bit line voltage, an entry indicating a bit line voltage to be applied to a corresponding separately-selectable set of NAND strings. A select line voltage sensing unit may be configured to sense select line threshold voltage and to compare a select line threshold voltage with a minimum threshold voltage; and a select line voltage adjustment unit may be configured to adjust select line voltage for a select line that has a select line threshold voltage that is less than the minimum threshold voltage. A table may record an entry for each separately-selectable set of NAND strings that has a select line threshold voltage that is less than the minimum threshold voltage, an entry in the table indicating a select line voltage to be applied to a select line in a corresponding separately-selectable set of NAND strings. An adaptive data encoding unit may encode data with variable redundancy prior to storage, the adaptive data encoding unit may be configured to apply a first redundancy scheme to data stored in separately-selectable sets of NAND strings that have bit line currents greater than the minimum current, and configured to apply a second redundancy scheme to data stored in separately-selectable sets of NAND strings that have bit line currents less than the minimum current. A table may record an entry for each separately-selectable set of NAND strings that has bit line currents less than the minimum current, an entry in the table indicating a redundancy scheme to be applied to data stored in a corresponding separately-selectable set of NAND strings.
An example of a three dimensional nonvolatile memory includes: a first separately-selectable set of NAND strings in a block, data in the first separately-selectable set of NAND strings encoded with a first level of redundancy; and a second separately-selectable set of NAND strings in the block, data in the second separately-selectable set of NAND strings encoded with a second level of redundancy that provides a higher level of error correction capability than the first level of redundancy.
An adaptive encoder/decoder may be configured to encode and decode data with a variable level of redundancy according to characteristics of separately-selectable sets of NAND strings in which data is stored. A bit line adjustment unit may be configured to apply a first bit line voltage to bit lines in the first separately-selectable set of NAND strings and to apply a second bit line voltage to bit lines in the second separately-selectable set of NAND strings. Configuration of the adaptive encoder/decoder, and configuration of the bit line adjustment unit to apply the first bit line voltage and the second bit line voltage, may be in response to testing of the first and second separately-selectable sets of NAND strings. A select line adjustment unit may be configured to apply a first select voltage to a first select line in the first separately-selectable set of NAND strings and to apply a second select voltage to a second select line in the second separately-selectable set of NAND strings. The first level of redundancy and the second level of redundancy may be determined according to characteristics of the first separately-selectable set of NAND strings and the second separately-selectable set of NAND strings respectively.
An example of a method of operating a three dimensional nonvolatile memory that includes multiple separately-selectable sets of NAND strings in a block, includes: measuring electrical current through a separately-selectable set of NAND strings having a common select line; comparing the electrical current with predetermined criteria; if the current does not meet the predetermined criteria then calculating one or more bit line voltage offsets; and subsequently, adjusting bit line voltages applied to bit lines connected to the separately-selectable set of NAND strings by the one or more bit line voltage offsets while other bit line voltages applied to other separately-selectable sets of NAND strings remain unadjusted.
The one or more bit line voltage offsets may be recorded for the separately-selectable set of NAND strings. The one or more bit line voltage offsets may be recorded in a table that contains a calculated bit line voltage offset for each separately-selectable set of NAND strings having a measured current that does not meet the predetermined criteria. An enhanced redundancy scheme may be applied to data stored in sets of strings that do not meet the predetermined criteria, the enhanced redundancy scheme providing a higher degree of error correction capacity than a regular redundancy scheme that is applied to data stored in sets of strings that meet the predetermined criteria. Select gate threshold voltage may be sensed for a select line in a separately-selectable set of NAND strings; the select gate threshold voltage may be compared with a minimum threshold voltage; a select line voltage offset may be calculated for a separately-selectable set of NAND strings that have a select line threshold voltage less than the minimum threshold voltage; and the select line voltage offset may be applied to select line voltages that are subsequently applied to the select line when accessing the separately-selectable set of NAND strings.
The select line voltage offset may be recorded for the separately-selectable set of NAND strings and additional select line voltage offsets may be recorded for other separately-selectable sets of NAND strings. Data to be stored in the separately-selectable set of NAND strings may be encoded using an enhanced encoding scheme.
Various aspects, advantages, features and embodiments are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings.
Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.
The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.
The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.
In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.
The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.
Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.
In other embodiments, types of memory other than the two dimensional and three dimensional exemplary structures described here may be used.
In practice, the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of a cell, a corresponding conduction current with respect to a fixed reference control gate voltage may be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.
Alternatively, instead of detecting the conduction current among a partitioned current window, it is possible to set the threshold voltage for a given memory state under test at the control gate and detect if the conduction current is lower or higher than a threshold current (cell-read reference current). In one implementation the detection of the conduction current relative to a threshold current is accomplished by examining the rate the conduction current is discharging through the capacitance of the bit line.
As can be seen from the description above, the more states a memory cell is made to store, the more finely divided is its threshold voltage window. For example, a memory device may have memory cells having a threshold voltage window that ranges from −1.5V to 5V. This provides a maximum width of 6.5V. If the memory cell is to store 16 states, each state may occupy from 200 mV to 300 mV in the threshold window. This will require higher precision in programming and reading operations in order to be able to achieve the required resolution.
When an addressed memory transistor 10 within a NAND string is read or is verified during programming, its control gate 30 is supplied with an appropriate voltage. At the same time, the rest of the non-addressed memory transistors in the NAND string 50 are fully turned on by application of sufficient voltage on their control gates. In this way, a conductive path is effectively created from the source of the individual memory transistor to the source terminal 54 of the NAND string and likewise for the drain of the individual memory transistor to the drain terminal 56 of the cell.
One difference between flash memory and other of types of memory is that a flash memory cell is generally programmed from the erased state. That is the floating gate is generally first emptied of charge. Programming then adds a desired amount of charge back to the floating gate. Flash memory does not generally support removing a portion of the charge from the floating gate to go from a more programmed state to a lesser one. This means that updated data cannot overwrite existing data and is instead written to a previous unwritten location.
Furthermore erasing is to empty all the charges from the floating gate and generally takes appreciable time. For that reason, it will be cumbersome and very slow to erase cell by cell or even page by page. In practice, the array of memory cells is divided into a large number of blocks of memory cells. As is common for flash EEPROM systems, the block is the unit of erase. That is, each block contains the minimum number of memory cells that are erased together. While aggregating a large number of cells in a block to be erased in parallel will improve erase performance, a large size block also entails dealing with a larger number of update and obsolete data.
Each block is typically divided into a number of physical pages. A logical page is a unit of programming or reading that contains a number of bits equal to the number of cells in a physical page. In a memory that stores one bit per cell (a Single Level Cell, or SLC″ memory), one physical page stores one logical page of data. In memories that store two bits per cell, a physical page stores two logical pages. The number of logical pages stored in a physical page thus reflects the number of bits stored per cell. The term Multi Level Cell, or “MLC” is generally used to refer to memories that store more than one bit per cell, including memories that store three bits per cell (TLC), four bits per cell, or more bits per cell. In one embodiment, the individual pages may be divided into segments and the segments may contain the fewest number of cells that are written at one time as a basic programming operation. One or more logical pages of data are typically stored in one row of memory cells. A page can store one or more sectors. A sector includes user data and overhead data.
A 2-bit code having a lower bit and an upper bit can be used to represent each of the four memory states. For example, the “E”, “A”, “B” and “C” states are respectively represented by “11”, “01”, “00” and ‘10”. The 2-bit data may be read from the memory by sensing in “full-sequence” mode where the two bits are sensed together by sensing relative to the read demarcation threshold values rV1, rV2 and rV3 in three sub-passes respectively.
3-D NAND structure
An alternative arrangement to a conventional two-dimensional (2-D) NAND array is a three-dimensional (3-D) array. In contrast to 2-D NAND arrays, which are formed along a planar surface of a semiconductor wafer, 3-D arrays extend up from the wafer surface and generally include stacks, or columns, of memory cells extending upwards. Various 3-D arrangements are possible. In one arrangement a NAND string is formed vertically with one end (e.g. source) at the wafer surface and the other end (e.g. drain) on top. In another arrangement a NAND string is formed in a U-shape so that both ends of the NAND string are accessible on top, thus facilitating connections between such strings.
As with planar NAND strings, select gates 705, 707, are located at either end of the string to allow the NAND string to be selectively connected to, or isolated from, external elements 709, 711. Such external elements are generally conductive lines such as common source lines or bit lines that serve large numbers of NAND strings. Vertical NAND strings may be operated in a similar manner to planar NAND strings and both Single Level Cell (SLC) and Multi Level Cell (MLC) operation is possible. While
Vertical NAND strings may be arranged to form a 3-D NAND array in various ways.
Common source lines “SL” connect to one end of each NAND string (opposite to the end that connects to the bit line). This may be considered the source end of the NAND string, with the bit line end being considered as the drain end of the NAND string. Common source lines may be connected so that all source lines for a block may be controlled together by a peripheral circuit. Thus, NAND strings of a block extend in parallel between bit lines on one end, and common source lines on the other end.
In some memory systems, bad blocks are detected and are marked so that they are not subsequently used for storage of user data. For example, detection and marking of bad blocks may be performed during factory testing. A bad block may be a block that fails to meet a set of criteria related to, for example, reading, writing, and/or erasing (e.g. failing to read, write, or erase within time limit), having an excessively high error rate or an excessive number of bad cells, and/or other criteria. If a particular die has more than a threshold number of bad blocks then the die may be discarded. In some cases, dies may be classified according to the number of bad blocks that they contain. Generally, dies with fewer bad blocks are preferable because data storage capacity of the memory is reduced by the number of bad blocks.
In some cases, blocks may have some inoperable components while other components remain operable. For example, one or more column in a block may be found to be inoperable and may be replaced by a spare column. Similarly, one or more rows of memory cells may be replaced in some cases. Small numbers of bad cells may be acceptable if the error rates resulting from such bad cells are low enough to allow correction by Error Correction Code (ECC) or some other form of redundancy.
In an example, blocks with multiple separately-selectable sets of strings that are identified as “bad” blocks are further tested to determine if there are operable sets of strings in the blocks (e.g. some sets of strings may meet test criteria even though the bock as a whole does not meet the criteria). While some failure modes may result in bad blocks that have no operable cells, other failure modes may affect a particular portion of a block and may leave at least some operable memory cells. Some failure modes may affect individual separately-selectable sets of NAND strings within a block while other sets of NAND strings remain operable. Testing of blocks identified as “bad” blocks may identify a number of blocks that contain a mix of operable and inoperable portions. In some cases, such partially-bad blocks may subsequently be used to store data thereby increasing the capacity of the memory. In some cases, portions of blocks that fail to meet testing criteria may be reconfigured so that that they meet the testing criteria. For example, a portion of a memory that fails testing when default operating parameters are used may pass when some modified operating parameters are used.
One failure mode may be encountered when a block or a portion of a block fails to erase. Such erase fails may be detected during testing or after some significant use (e.g. after a block has been used to store user data for a period of time). In general, after a block is subject to an erase step, an erase-verify step is used to determine if memory cells are in the erased condition, or if further erasing is needed. While an erase step may apply erase conditions to all memory cells of a block so that the block is erased as a unit, erase-verify may be applied to a portion of the block. For example, one separately-selectable set of NAND strings in a block may be selected for erase-verify at a time. By applying appropriate select and deselect voltages to select lines of a block, a particular set of NAND strings may be selected while other sets of NAND strings are deselected. Appropriate erase-verify voltages may be applied to all word lines so that all cells are turned on, which should allow current flow through NAND strings. This current may be measured to determine if the memory cells are erased. If the number of NAND strings in a selected set of NAND strings that are not adequately erased (e.g. that do not have a current greater than a minimum current) is greater than a maximum allowable number then another erase step may be performed, followed by another erase-verify step. In general, erase and erase-verify steps are repeated until a maximum time or a maximum number of cycles is reached. When such a maximum is reached an erase failure may be reported and the set of NAND strings may be considered bad (and the block may be considered a bad block in some cases).
In some cases, erase failure occurs because memory cells fail to erase (remain programmed) even after a number of erase cycles. In other cases, an erase failure may occur for other reasons. A NAND string may fail an erase-verify step even though memory cells are adequately erased. For example, current through a NAND string may remain low because of some component other than a memory cell contributes significantly to the resistance of the NAND string causing current through the NAND string to remain below a minimum current. For example, select transistors may contribute significant resistance in some cases. In some cases, connections at ends of NAND strings may contribute significant resistance. For example, there may be poor connections where NAND strings connect to a common source or to global bit lines, which may provide a relatively high resistance that reduces current flow through a NAND string.
In some cases, low current flow through NAND strings may be overcome by applying higher bit line voltage. Where a default bit line voltage fails to generate a required current flow due to some resistance, an increased bit line voltage may be enough to provide the required current flow according to the equation V=IR. Thus, one solution may include applying a higher bit line voltage to the global bit line of a NAND string that has low current flow. This may be done on a bit line by bit line basis where a relatively small number (e.g. fewer than a threshold number) of NAND strings in a separately-selectable set of NAND strings have low current flow. In some memory systems, bit lines are grouped into columns, where a column may include, for example, 8, 16, 32 or more bit lines. Higher bit line voltage may be applied on a column by column basis. In some cases, where a relatively large number of NAND strings (e.g. greater than a threshold number) in a separately-selectable set of NAND strings have low flow, then increased bit line voltage may be applied to all NAND strings in the set of NAND strings. A record may be maintained to indicate that modified bit line voltages are to be applied when accessing a separately-selectable set of NAND stings. A single increased bit line voltage may be used throughout such a set, or different increased bit line voltages may be used for different columns or for individual NAND strings, e.g. a set of different bit line voltage offsets may be obtained to adjust different bit line voltages to provide adequate current. A record may have a single entry for a set of separately-selectable NAND strings or may have an entry for a column, which may include multiple bit lines, or may have individual entries for bit lines that require increased voltage. Entries may be one-bit entries that indicate an increased bit line voltage, or may be larger entries that indicate the magnitude of an increased bit line voltage.
Testing may be performed under different conditions and test results may be compared with various criteria including current flow under different conditions. For example, as shown in
In some cases, increased resistance of a unit (e.g. NAND string resistance) may be caused by select transistors. Generally, because select lines are shared by all NAND strings in a separately-selectable set of NAND strings, select line issues may affect most or all NAND strings of a separately-selectable set of NAND strings. In an example, a set of NAND strings that shows a high number of NAND strings with low current (high resistance) is tested to see if higher select line voltage may overcome the problem. Increased select line voltages may be tested to see if the number of high resistance NAND strings can be reduced to an acceptable number. If increased select line voltage reduces the number of high resistance NAND strings sufficiently, then this indicates that select transistors are a substantial cause of resistance. Subsequently, access to the set of NAND strings may use an increased select line voltage for at least one select line. A record may be maintained to indicate that an increased select line voltage is required for this separately-selectable set of NAND strings and subsequent access operations may use the increased select line voltage accordingly. In some cases, a single increased select line voltage may be used for any separately-selectable set of NAND strings that can be fixed in this way. In other cases, select line voltage may be increased by different amounts according to results of testing. It may be preferable to use lower select line voltages where possible so that a range of select line voltages may be applied depending on the severity of the problem encountered in different separately-selectable sets of NAND strings.
In some cases, a portion of a block may be reclaimed by combining approaches, e.g. by applying increased select line voltage and increasing bit line voltage. It will be understood that these approaches are not exclusive and may be applied in any manner that is effective including by combining with other approaches.
In some examples, where a portion of a block is suspected of being defective in some way, additional steps may be taken to protect the data stored in such a portion. For example, a higher level of redundancy may be applied to data stored in such a portion than other portions. A memory system that encodes data using a default encoding scheme with a certain error correction capacity may encode data for storage in a suspect area with an enhanced encoding scheme what has a higher error correction capacity. For example, a first error correction code (ECC) scheme may be applied as a default scheme to data stored in the memory array, while a second ECC scheme with a higher redundancy ratio (and thus greater error correction capacity) may be applied to data stored in suspect areas. In some cases an additional redundancy scheme may be applied to data stored in suspect portions. For example, in addition to a default ECC scheme, another redundancy scheme may be added to particular portions of data. An example of such an additional scheme is an exclusive OR (XOR) scheme that is applied to a number of portions of data, and which allows one of the portions to be recalculated from the other portions and the redundancy data. An increased redundancy ratio may be the result of an enhanced redundancy scheme or of an additional redundancy scheme that is selectively applied to data in suspect areas.
An area may be considered suspect and data stored in the area may be subject to additional measures for a number of reasons. Where a portion of a block, such as a separately-selectable set of NAND strings, fails to meet some criteria such as having a high number of NAND strings with low current flow, the portion may be considered suspect. A higher than usual select line voltage may be used and/or a higher than usual bit line voltage may be applied and/or a higher redundancy ratio may be applied to stored data. A table may be maintained that indicates which portions of a block should have data encoded with an increased redundancy ratio. In some cases, such a table may be combined with a table that indicates other operating parameters such as increased bit line voltage and/or increased select line voltage. Where a block contains suspect portions, access time may be increased, e.g. because of additional encoding and configuration time, and the risk of data loss may be higher. Therefore, such blocks may be maintained as reserve blocks that are only used when there are no good blocks available. Thus, user data may only be stored in such blocks after all good blocks are used so that performance is not affected.
Subsequently, when the finger is accessed, a determination is made as to whether the access is a program operation 525. If it is a program operation then conditions are adjusted 527 for the word line (WL) being programmed, e.g. by increasing one or more select line voltages and/or increasing one or more bit line voltages and/or applying a higher redundancy ratio to the data being stored by providing additional parity data in the finger 531.
If the operation is not a program operation, then a determination is made as to whether it is a host read operation 535. If it is a host read operation then select gate (SG) and/or bit line (BL) voltages may be adjusted 537 to perform the read. Adjustment may be indicated by a record entry. After data is read and returned to the host, data may be relocated 539 to a safer location (e.g. a finger that does not require adjusted voltages).
If the operation is not a program or host write operation then a determination is made as to whether it is an erase operation 545. If it is an erase operation then select gate (SG) and/or bit line (BL) voltages may be adjusted 547. Adjustment may be indicated by a record entry. The erase operation then proceeds 549 with the adjusted voltages.
If the operation is not a program, host write, or erase operation, then a read scrub operation is performed 555 that measures the health of the finger, e.g. measures the number of cells that have some level of disturbance and may measure the amount of disturbance. Read scrub may be performed with modified parameters such as select line voltages and bit line voltages. The data is relocated 557 to another location (using ECC to correct any errors in the data).
In addition to the variation from string-to-string there may be other variation in a NAND memory such as this. For example, channels of NAND strings are formed in memory holes in this example and the diameter of such a memory hole generally decreases with increasing depth because of etch chemistry. Thus, there may be predictable differences between memory cells as a function of height above the substrate. In some cases, such differences may be detected and some adjustment may be made according to memory hole diameter. Measurement and adjustment is not limited to sets of strings or any other unit and may be applied to a variety of memories other than three dimensional NAND flash memories.
In addition to NAND flash memory, various other memories may include separately-selectable portions in a block and may benefit from structures and techniques described here. Referring initially to
A circuit for selectively connecting internal memory elements with external data circuits may be formed in a semiconductor substrate 13. In this specific example, a two-dimensional array of select or switching devices Qxy are utilized, where x gives a relative position of the device in the x-direction and y its relative position in the y-direction. The individual devices Qxy may be a select gate or select transistor, as examples. Global bit lines (GBLx) are elongated in the y-direction and have relative positions in the x-direction that are indicated by the subscript. The global bit lines (GBLx) are individually connectable with the source or drain of the select devices Q having the same position in the x-direction, although during reading and also typically programming only one select device connected with a specific global bit line is turned on at time. The other of the source or drain of the individual select devices Q is connected with one of the local bit lines (LBLxy). The local bit lines are elongated vertically, in the z-direction, and form a regular two-dimensional array in the x (row) and y (column) directions.
In order to connect one set (in this example, designated as one row) of local bit lines with corresponding global bit lines, control gate lines SGy are elongated in the x-direction and connect with control terminals (gates) of a single row of select devices Qxy having a common position in the y-direction. The select devices Qxy therefore connect one row of local bit lines (LBLxy) across the x-direction (having the same position in the y-direction) at a time to corresponding ones of the global bit-lines (GBLx), depending upon which of the control gate lines SGy receives a voltage that turns on the select devices to which it is connected. The remaining control gate lines receive voltages that keep their connected select devices off. It may be noted that since only one select device (Qxy) is used with each of the local bit lines (LBLxy), the pitch of the array across the semiconductor substrate in both x and y-directions may be made very small, and thus the density of the memory storage elements large.
Memory storage elements Mzxy are formed in a plurality of planes positioned at different distances in the z-direction above the substrate 13. Two planes 1 and 2 are illustrated in
Each “plane” of the three-dimensional memory cell structure is typically formed of at least two layers, one in which the conductive word lines WLzy are positioned and another of a dielectric material that electrically isolates the planes from each other. Additional layers may also be present in each plane, depending for example on the structure of the memory elements Mzxy. The planes are stacked on top of each other on a semiconductor substrate with the local bit lines LBLxy being connected with storage elements Mzxy of each plane through which the local bit lines extend.
Referring to
Each bit line pillar is connected to one of a set of global bit lines (GBL) in the silicon substrate running in the y-direction at the same pitch as the pillar spacing through the select devices (Qxy) formed in the substrate whose gates are driven by the select gate lines (SG) elongated in the x-direction, which are also formed in the substrate. The switching devices Qxy may be conventional CMOS transistors (or vertical npn transistors) and may be fabricated using the same process as used to form other conventional circuitry. In the case of using npn transistors instead of MOS transistors, the select gate (SG) lines are replaced with the base contact electrode lines elongated in the x-direction. Also fabricated in the substrate but not shown in
There is one select gate line (SG) for each row of local bit line pillars in the x-direction and one select device (Q) for each individual local bit line (LBL). Thus, for example, SG3 is a select gate line that controls select devices Q13, Q23, and additional select devices (not shown) along the x-direction. The local bit lines LBL13, LBL23, and additional local bit lines (not shown) along the x-direction and the memory elements connected to these local bit lines form a portion of the memory that is separately-selectable. In some cases, different separately-selectable portions of a memory may have different characteristics which may be discovered by performing some testing. For example, it can be seen that global bit lines extend in the y-direction in
Each vertical strip of non-volatile memory element (NVM) material is sandwiched between the vertical local bit lines (LBL) and a plurality of word lines (WL) vertically stacked in all the planes. Preferably the NVM material is present between the local bit lines (LBL) in the x-direction. A memory storage element (M) is located at each intersection of a word line (WL) and a local bit line (LBL). Where the memory storage element (M) is a resistive element, a small region of the NVM material between an intersecting local bit line (LBL) and word line (WL) may be controllably alternated between conductive (set) and non-conductive (reset) states by appropriate voltages applied to the intersecting lines.
There may also be a parasitic NVM element formed between the LBL and the dielectric between planes. By choosing the thickness of the dielectric strips to be large compared to the thickness of the NVM material layer (that is, the spacing between the local bit lines and the word lines), a field caused by differing voltages between word lines in the same vertical word line stack can be made small enough so that the parasitic element never conducts a significant amount of current. Similarly, in other embodiments, the non-conducting NVM material may be left in place between adjacent local bit lines if the operating voltages between the adjacent LBLs remain below the programming threshold.
Various materials may be used as NVM materials. The material used to form resistive memory elements (e.g. used to form memory elements Mzxy in the array of
Metal oxides are characterized by being insulating when initially deposited. One suitable metal oxide is a titanium oxide (TiOx). In the example of
But when a large negative voltage (such as 1.5 volt) is applied across the structure, the oxygen vacancies drift toward the top electrode and, as a result, the potential barrier Pt/TiO2 is reduced and a relatively high current can flow through the structure. The device is then in its low resistance (conductive) state. Experiments reported by others have shown that conduction occurs in filament-like regions of the TiO2, perhaps along grain boundaries.
The conductive path is broken by applying a large positive voltage across the structure of
While this specific conduction mechanism may not apply to all metal oxides, as a group, they have a similar behavior: transition from a low conductive state to a high conductive occurs state when appropriate voltages are applied, and the two states are non-volatile. Examples of other materials include HfOx, ZrOx, WOx, NiOx, CoOx, CoalOx, MnOx, ZnMn2O4, ZnOx, TaOx, NbOx, HfSiOx, HfAlOx. Suitable top electrodes include metals with a high work function (typically >4.5 eV) capable to getter oxygen in contact with the metal oxide to create oxygen vacancies at the contact. Some examples are TaCN, TiCN, Ru, RuO, Pt, Ti rich TiOx, TiAlN, TaAlN, TiSiN, TaSiN, IrO2. Suitable materials for the bottom electrode are any conducting oxygen rich material such as Ti(O)N, Ta(O)N, TiN and TaN. The thicknesses of the electrodes are typically 1 nm or greater. Thicknesses of the metal oxide are generally in the range of 5 nm to 50 nm.
Another class of materials suitable for the memory storage elements is solid electrolytes but since they are electrically conductive when deposited, individual memory elements need to be formed and isolated from one another. Solid electrolytes are somewhat similar to the metal oxides, and the conduction mechanism is assumed to be the formation of a metallic filament between the top and bottom electrode. In this structure the filament is formed by dissolving ions from one electrode (the oxidizable electrode) into the body of the cell (the solid electrolyte). In one example, the solid electrolyte contains silver ions or copper ions, and the oxidizable electrode is preferably a metal intercalated in a transition metal sulfide or selenide material such as Ax(MB2)1-x, where A is Ag or Cu, B is S or Se, and M is a transition metal such as Ta, V, or Ti, and x ranges from about 0.1 to about 0.7. Such a composition minimizes oxidizing unwanted material into the solid electrolyte. One example of such a composition is Agx(TaS2)1-x. Alternate composition materials include α-AgI. The other electrode (the indifferent or neutral electrode) should be a good electrical conductor while remaining insoluble in the solid electrolyte material. Examples include metals and compounds such as W, Ni, Mo, Pt, metal silicides, and the like.
Examples of solid electrolytes materials are: TaO, GeSe or GeS. Other systems suitable for use as solid electrolyte cells are: Cu/TaO/W, Ag/GeSe/W, Cu/GeSe/W, Cu/GeS/W, and Ag/GeS/W, where the first material is the oxidizable electrode, the middle material is the solid electrolyte, and the third material is the indifferent (neutral) electrode. Typical thicknesses of the solid electrolyte are between 30 nm and 100 nm.
In recent years, carbon has been extensively studied as a non-volatile memory material. As a non-volatile memory element, carbon is usually used in two forms, conductive (or grapheme like-carbon) and insulating (or amorphous carbon). The difference in the two types of carbon material is the content of the carbon chemical bonds, so called sp2 and sp3 hybridizations. In the sp3 configuration, the carbon valence electrons are kept in strong covalent bonds and as a result the sp3 hybridization is non-conductive. Carbon films in which the sp3 configuration dominates, are commonly referred to as tetrahedral-amorphous carbon, or diamond like. In the sp2 configuration, not all the carbon valence electrons are kept in covalent bonds. The weak tight electrons (phi bonds) contribute to the electrical conduction making the mostly sp2 configuration a conductive carbon material. The operation of the carbon resistive switching nonvolatile memories is based on the fact that it is possible to transform the sp3 configuration to the sp2 configuration by applying appropriate current (or voltage) pulses to the carbon structure. For example, when a very short (1-5 ns) high amplitude voltage pulse is applied across the material, the conductance is greatly reduced as the material sp2 changes into an sp3 form (“reset” state). It has been theorized that the high local temperatures generated by this pulse causes disorder in the material and if the pulse is very short, the carbon “quenches” in an amorphous state (sp3 hybridization). On the other hand, when in the reset state, applying a lower voltage for a longer time (˜300 nsec) causes part of the material to change into the sp2 form (“set” state). The carbon resistance switching non-volatile memory elements have a capacitor like configuration where the top and bottom electrodes are made of high temperature melting point metals like W, Pd, Pt and TaN.
There has been significant attention recently to the application of carbon nanotubes (CNTs) as a non-volatile memory material. A (single walled) carbon nanotube is a hollow cylinder of carbon, typically a rolled and self-closing sheet one carbon atom thick, with a typical diameter of about 1-2 nm and a length hundreds of times greater. Such nanotubes can demonstrate very high conductivity, and various proposals have been made regarding compatibility with integrated circuit fabrication. It has been proposed to encapsulate “short” CNT's within an inert binder matrix to form a fabric of CNT's. These can be deposited on a silicon wafer using a spin-on or spray coating, and as applied the CNT's have a random orientation with respect to each other. When an electric field is applied across this fabric, the CNT's tend to flex or align themselves such that the conductivity of the fabric is changed. The switching mechanism from low-to-high resistance and the opposite is not well understood. As in the other carbon based resistive switching non-volatile memories, the CNT based memories have capacitor-like configurations with top and bottom electrodes made of high melting point metals such as those mentioned above.
Yet another class of materials suitable for the memory storage elements is phase-change materials. A preferred group of phase-change materials includes chalcogenide glasses, often of a composition GexSbyTez, where preferably x=2, y=2 and z=5. GeSb has also been found to be useful. Other materials include AgInSbTe, GeTe, GaSb, BaSbTe, InSbTe and various other combinations of these basic elements. Thicknesses are generally in the range of 1 nm to 500 nm. The generally accepted explanation for the switching mechanism is that when a high energy pulse is applied for a very short time to cause a region of the material to melt, the material “quenches” in an amorphous state, which is a low conductive state. When a lower energy pulse is applied for a longer time such that the temperature remains above the crystallization temperature but below the melting temperature, the material crystallizes to form poly-crystal phases of high conductivity. These devices are often fabricated using sub-lithographic pillars, integrated with heater electrodes. Often the localized region undergoing the phase change may be designed to correspond to a transition over a step edge, or a region where the material crosses over a slot etched in a low thermal conductivity material. The contacting electrodes may be any high melting metal such as TiN, W, WN and TaN in thicknesses from 1 nm to 500 nm.
It will be noted that the memory materials in most of the foregoing examples utilize electrodes on either side thereof whose compositions are specifically selected. In embodiments of the three-dimensional memory array herein where the word lines (WL) and/or local bit lines (LBL) also form these electrodes by direct contact with the memory material, those lines are preferably made of the conductive materials described above. In embodiments using additional conductive segments for at least one of the two memory element electrodes, those segments are therefore made of the materials described above for the memory element electrodes.
Steering elements are commonly incorporated into controllable resistance types of memory storage elements. Steering elements can be a transistor or a diode. Although an advantage of the three-dimensional architecture described herein is that such steering elements are not necessary, there may be specific configurations where it is desirable to include steering elements. The diode can be a p-n junction (not necessarily of silicon), a metal/insulator/insulator/metal (MIIM), or a Schottky type metal/semiconductor contact but can alternately be a solid electrolyte element. A characteristic of this type of diode is that for correct operation in a memory array, it is necessary to be switched “on” and “off” during each address operation. Until the memory element is addressed, the diode is in the high resistance state (“off” state) and “shields” the resistive memory element from disturb voltages. To access a resistive memory element, three different operations are needed: a) convert the diode from high resistance to low resistance, b) program, read, or reset (erase) the memory element by application of appropriate voltages across or currents through the diode, and c) reset (erase) the diode. In some embodiments one or more of these operations can be combined into the same step. Resetting the diode may be accomplished by applying a reverse voltage to the memory element including a diode, which causes the diode filament to collapse and the diode to return to the high resistance state.
For simplicity the above description has considered the simplest case of storing one data value within each cell: each cell is either reset or set and holds one bit of data. However, the techniques of the present application are not limited to this simple case. By using various values of ON resistance and designing the sense amplifiers to be able to discriminate between several of such values, each memory element, of whatever memory element type, may be configured to hold multiple-bits of data in a multiple-level cell (MLC).
A suitable adjustment scheme may be stored in some manner so that adjustment is performed whenever accessing a corresponding portion of the memory array. For example, voltage offsets (offsets from default read voltage, write voltage, erase voltage, etc.) may be stored in a table that includes entries for different portions of the memory array. Such a table may be stored in the nonvolatile memory and may be accessed when needed. In some examples, an adjustment unit is located in a memory controller that is connected to one or more memory dies over a memory bus. A table, or tables, may record voltage offsets to use when accessing different portions of blocks in different memory dies. Such a table may be recorded in nonvolatile memory and may be read by the controller when needed (e.g. loaded into RAM or other easily accessed memory).
In addition to modifying voltages used to access portions of a memory array, other adjustment may be made. For example, some portions of a memory may be identified as having a higher risk of data loss (e.g. because of data retention problems, or other issues). When such portions are identified, some adjustment may be made to reduce risk of loss. For example, an enhanced redundancy scheme may be used. In general, ECC schemes with more redundancy allow a larger number of errors to be corrected and thus provide a lower risk of data loss. However, such enhanced redundancy requires more storage space. Where characteristics of different portions of the memory array are known, redundancy may be adapted on a portion-by-portion basis so that adequate redundancy is provided in a given portion based on the risk in that portion.
Adjustment may be made according to various characteristics of a portion of a memory array including series resistance as discussed above. Such adjustment may be made in a static manner so that offsets are calculated once and are then used throughout the life of the product. Alternatively, adjustment may be made in a dynamic manner so that offsets are recalculated as needed during the life of the product. For example, a table of offsets may be updated at some intervals based on time, number of write-erase cycles, and/or other factors. Additionally, adjustment may be made according to environmental or other factors.
In one example, temperature may be considered when adjusting operating parameters. In some memories memory characteristics change with temperature and some adjustment of operating parameters may be made accordingly. For example, if temperature exceeds a threshold then different operating parameters (e.g. read voltage, write voltage, erase voltage, etc.) may be used. Such adjustment may be applied uniformly for all portions of a memory array where it is assumed that all portions are at substantially the same temperature (e.g. based on a single temperature measurement in a memory die, or in a memory controller die, or other die). Alternatively, multiple temperature measurements may allow different temperature adjustment for different portions of a memory array. For example, different memory dies may have temperature sensors that provide temperatures for their respective dies. Adjustment may then be performed on a die basis.
While the example of
When a voltage is applied to a line in an arrangement like that shown in
Suitable voltages and/or other operating parameters may be recorded for different portions. For example, one or more offsets may be applied to different portions and offsets may be recorded in a table or other recording structure. As in prior examples, adjustment may also be made according to environmental factors such as temperature. Different redundancy may be applied to data in different portions of the memory array according to characteristics of the respective portions.
Various methods may be used to operate a memory as described above.
The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the attached claims. Many modifications and variations are possible in light of the above teaching.
This application is a continuation-in-part of U.S. patent application Ser. No. 15/190,749, filed on Jun. 23, 2016, which is a continuation of U.S. patent application Ser. No. 14/861,951, filed on Sep. 22, 2015, now U.S. Pat. No. 9,401,216.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14861951 | Sep 2015 | US |
| Child | 15190749 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15190749 | Jun 2016 | US |
| Child | 15276635 | US |
