Claims
- 1. A semiconductor device structure, comprising:a semiconductor substrate including at least one active device region; a stacked capacitor structure disposed above said semiconductor substrate, including a portion that extends substantially over at least one transistor gate and includes at least one oxidized lateral edge that extends substantially to an edge of an interconnect location and is in electrical isolation from said interconnect location; and a first interconnect element comprising aluminum extending adjacent said at least one lateral edge of said stacked capacitor structure and in electrical communication with said at least one active device region through a second interconnect element comprising a metal silicide, said at least one active device region being substantially covered by said second interconnect element and at least a side wall spacer of said transistor gate; and at least one bit line formed from the same aluminum-comprising material as said first interconnect element and extending over said stacked capacitor structure, said at least one bit line and said first interconnect element comprising a unitary structure with no discernable boundary being located between said first interconnect element and said at least one bit line.
- 2. The semiconductor device structure of claim 1, wherein said first interconnect element is disposed within a contact aperture adjacent said at least one transistor gate.
- 3. The semiconductor device structure of claim 1, further comprising a buried metal diffusion layer adjacent said at least one active device region.
- 4. The semiconductor device structure of claim 3, wherein said buried metal diffusion layer comprises a metal silicide.
- 5. The semiconductor device structure of claim 4, wherein said metal silicide is selected from titanium suicide and tungsten silicide.
- 6. The semiconductor device structure of claim 5, wherein said buried metal diffusion layer further comprises a metal nitride layer adjacent said metal silicide.
- 7. The semiconductor device structure of claim 1, further comprising a metal silicide layer disposed above said at least one active device region.
- 8. The semiconductor device structure of claim 7, wherein said metal silicide is selected from titanium silicide layer and tungsten silicide.
- 9. The semiconductor device structure of claim 7, further comprising a metal nitride adjacent said metal silicide layer.
- 10. The semiconductor device structure of claim 9, wherein said metal nitride comprises titanium nitride or tungsten nitride.
- 11. The semiconductor device structure of claim 9, wherein said metal nitride contacts said first interconnect element.
- 12. The semiconductor device structure of claim 9, wherein said metal nitride is disposed between said metal silicide layer and said first interconnect element.
- 13. The semiconductor device structure of claim 1, wherein said first interconnect element extends through said stacked capacitor structure.
- 14. The semiconductor device structure of claim 1, wherein said first interconnect element is electrically insulated from said stacked capacitor structure.
- 15. The semiconductor device structure of claim 1, wherein said at least one active device region comprises a source or a drain.
- 16. The semiconductor device structure of claim 1, wherein said first interconnect element has a contact resistance of less than about 5 μΩ-cm.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional of application Ser. No. 09/102,331, filed Jun. 22, 1998, now U.S. Pat. No. 6,165,863, issued Dec. 26, 2000.
US Referenced Citations (25)
Non-Patent Literature Citations (1)
Entry |
Tsukamoto, et al., 1997 Symposium on VLSI Technology Digest of Technical Papers “.25μm W-Polycide Dual Gate and Buried Metal on Diffusion Layer (BMD) Technology for DRAM-Embedded Logic Devices” pp. 23-24. |