APPARATUS AND METHODS RELATED TO COPPER PLATING OF WAFERS

BACKGROUND

1. Field

The present disclosure generally relates to copper plating of semiconductor wafers.

2. Description of the Related Art

In some semiconductor applications, an entire side of a wafer can be plated. Quality of the resulting plated layer such as a copper layer is desirable. Such quality can include, for example, desired thickness and limited or absence of oxidation.

SUMMARY

In accordance with a number of implementations, the present disclosure relates to a method for copper plating a wafer. The method includes estimating a change in surface area exposed on a side of the wafer, with the estimated change being based at least in part on a number of vias formed on the side of the wafer. The method further includes adjusting a plating parameter based on the estimated change.

In some embodiments, the vias can include through-wafer vias (TWVs). Each of the TWVs can be modeled as a trapezoidal prism to calculate an exposed surface area of the TWV. The exposed surface area of the TWV can be corrected with an oval approximation for a rectangular sectional shape of the trapezoidal prism. The exposed surface area of the TWV can be further corrected based on different likely plating thicknesses corresponding to different portions of the TWV. The exposed surface area of the TWV can be further corrected based on an estimated roughness inside the TWV.

In some embodiments, the plating parameter can include a plating time interval. The method can further include selecting the plating time interval to yield a desired plating thickness on the side of the wafer. In some applications, the side of the wafer can be a backside of the wafer. Such a wafer can include, for example, gallium arsenide (GaAs).

In some embodiments the method can further include mounting the wafer on a fixture to yield a wafer-fixture assembly. The method can further include loading the wafer-fixture assembly into a plating tool such that the fixture facilitates immersion of the wafer at a desired depth in a plating solution. The method can further include performing a plating operation for the plating time interval to yield a plated copper layer. The method can further include rinsing and drying the wafer. The method can further include providing a holding environment for the rinsed and dried wafer. The holding environment can be substantially free of an airflow to reduce oxidation of the plated copper layer.

In a number of teachings, the present disclosure relates to a copper plating system that includes a plating tool configured to receive a wafer and form a plated copper layer on a side of the wafer. The plating system further includes a processor configured to provide control functionality for the plating tool. The processor is further configured to estimate a change in surface area exposed on the side of the wafer, with the estimated change being based at least in part on a number of vias formed on the side of the wafer. The processor is further configured to facilitate adjustment of a plating parameter based on the estimated change.

In some embodiments, the plating system can further include a computer-readable medium (CRM) in communication with the processor, with the CRM including data utilized by the processor for calculating the estimated change. The CRM can further include at least some algorithm utilized by the processor for the calculation.

According to some implementations, the present disclosure relates to a copper plating apparatus that includes a plating tool configured to receive a wafer and form a plated copper layer on a side of the wafer. The apparatus further includes a rinse and dry system configured to clean the wafer after the formation of the plated copper layer. The apparatus further includes a holding device configured to hold the cleaned wafer. The apparatus further includes a cabinet surrounding at least the holding device. The cabinet is configured to provide an environment that is substantially free of air flow to reduce oxidation of the plated copper layer.

In some embodiments, the apparatus can further include a robotic system configured to provide automated movements of the wafer.

For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows examples of shifts in sheet resistance values for groups of wafers plated with copper.

FIG. 2 shows a photograph of a cross section of an example through-wafer via partially filled with plated metal.

FIGS. 3A and 3B show that the through-wafer via of FIG. 2 can be modeled as a rectangular sectional shape.

FIG. 4 shows that a correction can be implemented so that the corrected shape more closely matches the actual via's horizontal shape.

FIG. 5 shows that a spike or particle on a sidewall of the via can be simulated by the surface area of a top portion of a cone.

FIG. 6 shows a plot of sheet resistance data from plated wafers with varying numbers of vias.

FIG. 7 shows an example of reduction in copper thickness variation among plated wafers by use of one or more features as described herein.

FIG. 8 shows a process that can be implemented to adjust a plating parameter such as plating time based on an estimate of increase in surface area due to vias.

FIG. 9 shows a plating system having one or more features as described herein.

FIGS. 10A and 10B show photographs of examples of oxidizing copper plating formed on wafers.

FIG. 11 shows an example of a plating tool with its head closed.

FIGS. 12A and 12B show side and plan views of a wafer mounted on a fixture to facilitate various processes.

FIG. 13 shows an example of how a rinsing operation can be performed on a plated wafer.

FIG. 14 shows an example of how air flow can exist in some wafer plating apparatus.

FIG. 15 shows that in some embodiments, a wafer plating apparatus can be configured to provide an environment that is substantially free of air flow to reduce oxidation of plated wafers.

DETAILED DESCRIPTION OF SOME EMBODIMENTS

The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

Disclosed are examples related to improved systems, apparatus and methods for plating of semiconductor wafers. Various examples are described in the context of copper plating; however, it will be understood that one or more features of the present disclosure can also be utilized for plating of other metals.

Examples Related to Improved Uniformity in Plating Thickness

While through-wafer-vias (TWVs) etched into the backside of semiconductor wafers appear to be very small, their combined surface area can have a significant impact on backside plated metal thickness. Described herein are examples related to estimation of plating thickness changes based on via geometry and the total number of vias etched in a wafer. Based on such estimation, process changes can be implemented to yield improved plating thickness uniformity.

In some semiconductor applications, control of backside plating thickness of wafers such as gallium arsenide (GaAs) wafers is desirable. Such backside plating can include, for example, formation of several microns of copper on a thin gold and nickel-vanadium film that acts as a copper diffusion barrier. Typically, there is no mask pattern on the wafer during plating; the entire backside and etched through-wafer-vias are plated as a single sheet film.

One would expect that plating relatively flat surfaces would result in consistent plating thicknesses from one wafer to the next. Likewise, plating thicknesses should be very close across different products. Traditionally, microscopic vias etched through a wafer were not thought to impact backside plating thickness control.

However, it was noticed that plating thicknesses fell into distinct product groups as inferred by measuring the sheet resistance (R_s) of the plated films. When the sheet resistance shifted, it generally shifted for all groups together, which indicated that the differences among products were generally independent of process variations attributed to plating bath and equipment parameter changes. Examples of such sheet resistance values shifting in groups are shown in FIG. 1.

It was noted that the main difference among the groups of products was the number of vias on the wafer. Some had many tens of thousands of vias, and others had several hundreds of thousands. As described herein, a model shows that not only the number of vias but also via configurations such as via dimensions, via surface roughness and wafer thickness can have a significant effect on backside plating thickness because of their collective impact on total wafer surface area. By incorporating these factors into the model, one can estimate the impact of each factor independently and determine what adjustment to plating time can be implemented to compensate for differences in plating thickness across different products.

FIG. 2 shows a cross section profile of an example through-wafer via partially filled with plated metal so as to yield a wineglass shape. Such an example via shape can be defined by a photoresist pattern and via etch process steps. A photomask can use a rectangular opening in a chrome plate to define each via. After exposure on a relatively low resolution contact aligner and after a develop process, the rectangle pattern in the resist typically has rounded corners.

Next, a bake step typically heats the resist to remove residual solvent and to improve adhesion, causing the vertical via profile to change. The top of resist typically contracts as solvent diffuses out from the bulk resist material, but the bottom of the resist is typically pinned by its adhesion to the substrate. At the end of the bake, the resist profile is typically sloped at the top of the via opening.

During the via etch step, gases remove the GaAs substrate material from locations not masked by the photoresist. Such an etch step creates holes in the substrate with near vertical walls. With longer etch time, the resist can slowly erode at the bottom of the via where the resist is typically the thinnest. The via opening typically increases in size allowing the etch gases to widen the etched hole dimension. Etching continues until a given recipe detects a reduction in etch byproduct material at the bottom of the via as tuned to coincide with desired length and width of the designed via dimensions. This gradual resist erosion and hole widening shifts the vertical via profile to a sloped via profile.

The surface profile and via dimensions can be utilized to estimate a surface area of a via. With one via modeled, the total surface area of the wafer can be calculated as the sum of the surface area of all vias and the surface area of the back of the wafer excluding via openings.

FIGS. 3A and 3B show that one can begin to model a via with an assumption that the via has a rectangular sectional shape. Accordingly, the etched via wall profile can be assumed to be linear, with the top (when viewed with the to-be-plated side facing upward) being larger than the bottom, such that the via forms a trapezoidal prism shape.

The top and bottom rectangle dimensions can be determined based on actual wafer measurements using, for example, a focused ion beam scanning electron microscope (FIB SEM), and the wafer thickness can provide the height of the trapezoidal prism. The sum of the areas of the sidewalls and bottom of such a prism can provide a rough estimate of the surface area of one via.

In some embodiments, one can implement one or more corrections to the foregoing model. For example, a first correction to the model can change the shape of the via opening from a rectangle to an ellipse. FIG. 4 shows an example of such an ellipse fit into the overall dimensions of the rectangle.

The ratio of the perimeter of the ellipse to the rectangle can be used as a correction factor to the surface area of the bottom of the via. The elliptical shape can be integrated from the bottom to the top of the via by multiplying this ratio by the total surface area of the via walls. For example, suppose that a rectangular opening of a via has dimensions of a=80 μm and b=20 μm so as to yield a rectangular circumference of 2a+2b=200 μm. Circumference of a perimeter of an ellipse having a major axis length of 2a and a minor axis length of 2b can be estimated as P≈2π√{square root over ([(a²+b²)/2)}. Accordingly, the foregoing example ellipse has an oval circumference of about 169.28 μm, to yield a perimeter ratio factor for oval/rectangle that is approximately 85%. An oval adjustment factor of 3% can be added to yield a total oval correction factor of approximately 88%. Based on the foregoing example, a first corrected via surface area can be calculated based on the dimensions of the rectangular via dimensions of FIGS. 3A and 3B.

One or more further correction changes can be implemented so that the corrected shape more closely matches the actual via horizontal shape. For example, FIG. 4 further shows a rectangular opening with rounded corners. It is noted that such adjustments can be based on observations of vias on wafers after they have been etched.

Since via openings are relatively deep and narrow, metal ions in a plating bath reach and plate the top of the via quickly while other ions take longer to diffuse toward the bottom of the via. Accordingly, plating thickness at the bottom of the via tends to be only a fraction of thickness on the back of the wafer. However, if the sidewall thickness is estimated as a linear change from the top of the via to the bottom, one can use an average thickness as an estimate. Such an average thickness can be obtained by, for example, thickness measurements obtained from FIB SEM cross sections. The foregoing estimates of the plating thickness at the bottom and sidewalls of the via can be applied as the second correction factor in the example model.

The thickness estimate of the sidewall multiplied by the via surface area generates the volume of plating for the via sidewalls. The plating thickness at the via floor can be multiplied by the bottom rounded rectangular area to determine the plating volume at the base of the via. Combining both of these volumetric results, one can establish a first estimate of the plated metal volume inside one via.

As described herein, backside plating volume can be determined by subtracting the surface area of all via openings from the backside wafer area and multiplying it by the plating thickness measured in wafer cross sections. Multiplying the total number of vias on the wafer by the plating volume of one via and adding this to the backside plating volume can equate to a first order estimate of plating volume for the wafer.

In the foregoing first order estimate, it is assumed that all plated surfaces are smooth. Roughness due to minor surface contamination as well as spikes on via walls can add considerable plating surface area. However, in some situations, it is not necessary to apply roughness estimates to the backside wafer surface, since such a backside surface is approximately common to all wafers being processed. Therefore, notable roughness locations on the plating surface area are the sidewalls of the vias. Further, such roughness only becomes a factor when processing wafers have differing numbers of vias.

To address the foregoing surface roughness in vias, one can utilize a third correction factor. A spike or particle on a sidewall can be simulated by the surface area of a top portion of a cone, as shown in FIG. 5. The average height of spikes and steps on via walls as seen in FIB cross section photos can be used to estimate the cone height. The density can be estimated by evaluating between spikes in the sidewall. This correction factor is multiplied by the total number of vias on the wafer.

After applying the foregoing correction factors, the model can be calibrated by collecting sheet resistance data from unplated wafers, plated wafers with no vias, and wafers with known numbers of vias. Plating thickness can be calculated from the sheet resistance data using the equation:

$\begin{matrix} Plated Cu Thk = \frac{ρ + Δ}{1 / (1 / R_{s (Plated Film)} - 1 / R_{s (Seed)})} & (1) \end{matrix}$

where ρ is the resistivity of the plated metal and Δ is a very small correction factor used to match the actual and theoretical resistances. A four point probe tool can be calibrated to ANSI resistance standards in a range of resistance measurements used by production and test wafers, and successfully pass a gauge repeatability and reproducability (GR&R) test completed over several days.

A plot of the sheet resistance data from plated wafers with varying numbers of vias is shown in FIG. 6. The open mask area ratio is a parameter that can be calculated by a mask design software. It can total all exposed mask area and divide the total by the total available mask area. This ratio correlates to the total number of vias on each product design; as the number of vias increases, the open mask area increases. FIG. 6 shows that when the number of vias on a product increase, the plated sheet resistance also increases.

Since wafers of different products were plated on the same equipment close in time, all other process factors during plating were fairly equal. Therefore, differences in plating thicknesses not only correlated to the number of vias on the wafer but they are believed to be the cause of the plating thickness changes, or at least contribute to such changes.

The foregoing observation allows one to compensate plating thicknesses by adjusting plating times. Since R_sdecreases linearly with plating time, one can assign plating times to each R_sresult by comparing the result to a reference product with a known number of vias and a fixed plating time. Based on this calculation, one can implement a correction to plating time as compared to the reference product when R_sresults were higher or lower than expected.

Rather than maintaining hundreds of recipes with different plating times optimized for each product, one can combine products into groups based on the number of vias for each product. Each group can be assigned one of five plating recipes with plating times adjusted to minimize or reduce group to group thickness variation. The plating time difference between groups was observed to be around 5%. With five plating groups the difference between the highest and lowest groups was observed to be near 20%.

Sheet resistance data collected on a large number (e.g., thousands) of plated wafers using many products with significantly different number of vias allowed one to fine tune original subjective correction factors, such as the oval adjustment factor and wafer roughness adjustment factor. Implementing these plating time changes resulted in >50% reduction in wafer to wafer backside copper thickness variation across all products. FIG. 7 shows an example of such a reduction in copper thickness variation over approximately five months.

In some embodiments, plating time selection can be automated so that new products are automatically processed with corrected plating time based on the open mask area defined by the corresponding mask design. One of five example plating recipes can be selected depending on which of the five bins the open mask area falls into when the product is first introduced into manufacturing.

As described herein, plating thickness variation is not just a function of process and equipment variation. For through-wafer-vias (TWVs), the mask design can also have a significant impact. Plating thickness can be affected by the total surface area on the wafer, including the plating surface area inside TWVs, previously considered to have a negligible impact. Experimental data revealed that different products receiving the same plating time had significantly different backside plating thicknesses and that these differences were generally not related to process or equipment parameter drift.

As described herein, one can estimate plating thickness differences across different products using a model that collects inputs of wafer thickness, number of vias on the wafer, via shape, plating thickness profile, via roughness and/or plating time. Such a model can be calibrated by collecting plated thickness measurements and sheet resistance data from product wafers with known numbers of vias. The model can utilize open mask area data calculated from the corresponding mask design software to translate an expected difference in sheet resistance into a recommended plating time change. After the plating time adjustment is applied on a large number of wafers (e.g., thousands) from different products, one can achieve more than a 50% reduction in backside plating thickness variation across all products.

FIG. 8 shows a process 100 that can be implemented to adjust a plating parameter such as plating time based on an estimate of increase in surface area due to vias. In block 102, an increase in surface area due to vias (e.g., through wafer vias) can be estimated. In block 104, a plating parameter such as plating time can be adjusted based on the estimated increase in surface area. In block 106, plating operation can be performed with the adjusted plating parameter.

FIG. 9 shows that in some embodiments, a plating system 110 can be configured to include one or more features as described herein. The plating system 110 can include a plating tool 112 configured to hold one or more wafers in a plating solution during a plating process. A solution system 114 can be configured to provide the plating solution to the plating tool 112. A wafer handling component 116 can be configured to handle wafers during various steps associated with the plating process. A power component 118 can be configured to provide power to the plating tool during the plating process.

In some embodiments, the plating system 110 can include a control system 120. Such a control system can include a processor 122; and such a processor can facilitate various operations associated with the plating process, including controlling of some or all of the process 100 of FIG. 8. The control system 120 can further include a computer-readable memory 124 configured to store information in a non-transitory manner to facilitate one or more features of the present disclosure.

Examples Related to Improved Plating Quality

When semiconductor wafers such as gallium arsenide (GaAs) wafers are plated with copper, a number of challenges arise. For example, copper (Cu) oxidation poses a significant challenge.

Copper oxidation can occur within minutes when a plated wafer is exposed to oxygen in ambient air, and even faster if the wafer is still wet or damp with copper bath solution or de-ionized water. There are different degrees of wafer oxidation depending on the amount of time the wafer is idle. FIGS. 10A and 10B show photographs of examples of oxidizing copper plating formed on wafers.

Oxidation of plated copper on wafers can be caused or related to a number of operating conditions. For example, handling of wafers can contribute to oxidation. Handling of wafers during the plating process can result in copper contamination in the form of crystal buildup on a robot end effector. Such contaminants can prevent wafers from making vacuum as they are pulled from plating chambers. Improper wafer rinsing can also contribure to copper oxidation. Laminar air flow and/or exhaust can also contribute to copper oxidation.

It is noted that a common equipment failure relates to copper contamination on the robot end effectors. Copper solution in crystal form can build up under the wafer ring seal and eventually find its way on to the end effector as it goes to retrieve the wafer. This can cause improper vacuum and inhibit the tool's automation. Such an event can in turn result in the wafer being oxidized before the tool can be fixed.

Another effect from the copper contamination can include damage to the robot end effectors. Over time, the robot end effectors can deteriorate from copper exposure to a point where the end effector seals become damaged. To eliminate or reduce the foregoing spread of the copper solution, more stringent maintenance and cleaning program can be implemented. In addition, a ceramic end effector can be utilized to better withstand exposure to copper solution.

In some situations, crystal build up can result from improper positioning of the Z-axis when the head is in the closed position. It has been observed that in some cases, the closed position is set too deep in the copper solution, thereby causing the copper solution to reach the back of the ring seals. As the heads open, such deep closed position can cause a scooping effect.

In some applications, design of a plating tool (e.g., 112 in FIG. 11) is such that one cannot see the depth of the wafer in the solution with the head closed. Instead, one may need to rely on a trial and error method to ensure that the wafer comes in contact with the bath meniscus for optimal plating. In some situations, however, such positioning of wafer can be over-compensated or cause damage to the tool.

To eliminate or reduce the foregoing guess work, a pyrex fixture can be utilized to better locate a depth height reference point. As shown in FIGS. 12A (side view) and 12B (plan view), such a fixture (152) can be dimensioned to be larger than the wafer 150. The wafer 150 can be mounted on the fixture 152 so as to expose the side (e.g., backside) to be copper plated. Such a mounted configuration can be utilized for a number of processing steps.

The pyrex fixture can be placed inside the chamber on top of a diffuser plate assembly and acts as a hard stop when setting the closed position. Such a configuration can ensure that the wafers (when in the closed position) are not too deep in the solution. As a result, one can better position the wafers to be plated while preventing or reducing copper solution from spreading to the backsides of the ring seals.

Wafers are typically rinsed after plating in the same chamber, using an in situ-rinse step. If wafers are not rinsed properly, oxidation of the plated copper can increase, and/or the copper bath can be diluted with rinse water. To achieve a desired rinse, a rinse water (e.g., de-ionized water stream) can be configured to be incident of a spinning wafer, and be deflected into a capture bowl instead of the copper bath. As shown in FIG. 13, such a configuration can be achieved by a water nozzle 160 being positioned and oriented relative to the wafer 150 (mounted on a fixture 152) appropriately such that the water stream 162 properly cleans the wafer.

After plating copper in the plating tool, each wafer is typically rinsed in-situ using a small stream of de-ionized water to remove most of the plating solution from the surface of the wafer. However, it was observed that wafers would oxidize to an orange color in less than about 20 seconds after being unloaded from the plating tool if the in-situ rinse was not set up correctly.

After such in-situ rinsing, plating wafers are typically loaded into a rinse head for more thorough rinsing and drying. However, oxidation continued on the dried wafers to a dark brown color as completed wafers sat in an unload cassette waiting for the rest of the lot to finish the plating process.

It was noticed that a plating cabinet design being utilized provides significant laminar flow across the upper cabinet deck, to accommodate a variety of end uses and materials such as strong acids, bases and solvents. High laminar flow is generally not required or desired in copper plating steps. In fact, such high laminar flow can be detrimental for copper plating bath steps.

The upper of the foregoing cabinet was designed with louvers that can be closed to block or reduce air flow. However, closing of such louvers still yielded significant air flow through a number of gaps. In FIG. 14, such a cabinet is depicted as 170, and is shown to include a plating tool 112 as described herein. An air flow such as a laminar air flow as in the foregoing example is depicted as 172.

In FIG. 15, the cabinet 170 can be configured so as to substantially eliminate air flow where the wafers are exposed for significant amount of time. Such a configuration can include, for example, substantially fully blocking the opening. The substantially blocked portion of the cabinet 170 is indicated as 174. When the air flow was substantially fully blocked, oxidation was significantly reduced.

It is noted that a combination of foregoign three changes can significantly improve wafer handling characteristics, and minimize or reduce the number of wafers impacted by wafer oxidation related events.

The present disclosure describes various features, no single one of which is solely responsible for the benefits described herein. It will be understood that various features described herein may be combined, modified, or omitted, as would be apparent to one of ordinary skill. Other combinations and sub-combinations than those specifically described herein will be apparent to one of ordinary skill, and are intended to form a part of this disclosure. Various methods are described herein in connection with various flowchart steps and/or phases. It will be understood that in many cases, certain steps and/or phases may be combined together such that multiple steps and/or phases shown in the flowcharts can be performed as a single step and/or phase. Also, certain steps and/or phases can be broken into additional sub-components to be performed separately. In some instances, the order of the steps and/or phases can be rearranged and certain steps and/or phases may be omitted entirely. Also, the methods described herein are to be understood to be open-ended, such that additional steps and/or phases to those shown and described herein can also be performed.

Some aspects of the systems and methods described herein can advantageously be implemented using, for example, computer software, hardware, firmware, or any combination of computer software, hardware, and firmware. Computer software can comprise computer executable code stored in a computer readable medium (e.g., non-transitory computer readable medium) that, when executed, performs the functions described herein. In some embodiments, computer-executable code is executed by one or more general purpose computer processors. A skilled artisan will appreciate, in light of this disclosure, that any feature or function that can be implemented using software to be executed on a general purpose computer can also be implemented using a different combination of hardware, software, or firmware. For example, such a module can be implemented completely in hardware using a combination of integrated circuits. Alternatively or additionally, such a feature or function can be implemented completely or partially using specialized computers designed to perform the particular functions described herein rather than by general purpose computers.

Multiple distributed computing devices can be substituted for any one computing device described herein. In such distributed embodiments, the functions of the one computing device are distributed (e.g., over a network) such that some functions are performed on each of the distributed computing devices.

Some embodiments may be described with reference to equations, algorithms, and/or flowchart illustrations. These methods may be implemented using computer program instructions executable on one or more computers. These methods may also be implemented as computer program products either separately, or as a component of an apparatus or system. In this regard, each equation, algorithm, block, or step of a flowchart, and combinations thereof, may be implemented by hardware, firmware, and/or software including one or more computer program instructions embodied in computer-readable program code logic. As will be appreciated, any such computer program instructions may be loaded onto one or more computers, including without limitation a general purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer(s) or other programmable processing device(s) implement the functions specified in the equations, algorithms, and/or flowcharts. It will also be understood that each equation, algorithm, and/or block in flowchart illustrations, and combinations thereof, may be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or combinations of special purpose hardware and computer-readable program code logic means.

Furthermore, computer program instructions, such as embodied in computer-readable program code logic, may also be stored in a computer readable memory (e.g., a non-transitory computer readable medium) that can direct one or more computers or other programmable processing devices to function in a particular manner, such that the instructions stored in the computer-readable memory implement the function(s) specified in the block(s) of the flowchart(s). The computer program instructions may also be loaded onto one or more computers or other programmable computing devices to cause a series of operational steps to be performed on the one or more computers or other programmable computing devices to produce a computer-implemented process such that the instructions which execute on the computer or other programmable processing apparatus provide steps for implementing the functions specified in the equation(s), algorithm(s), and/or block(s) of the flowchart(s).

Some or all of the methods and tasks described herein may be performed and fully automated by a computer system. The computer system may, in some cases, include multiple distinct computers or computing devices (e.g., physical servers, workstations, storage arrays, etc.) that communicate and interoperate over a network to perform the described functions. Each such computing device typically includes a processor (or multiple processors) that executes program instructions or modules stored in a memory or other non-transitory computer-readable storage medium or device. The various functions disclosed herein may be embodied in such program instructions, although some or all of the disclosed functions may alternatively be implemented in application-specific circuitry (e.g., ASICs or FPGAs) of the computer system. Where the computer system includes multiple computing devices, these devices may, but need not, be co-located. The results of the disclosed methods and tasks may be persistently stored by transforming physical storage devices, such as solid state memory chips and/or magnetic disks, into a different state.

Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

The disclosure is not intended to be limited to the implementations shown herein. Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. The teachings of the invention provided herein can be applied to other methods and systems, and are not limited to the methods and systems described above, and elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

APPARATUS AND METHODS RELATED TO COPPER PLATING OF WAFERS

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