Apparatus for direct plating on resistive liners

FIELD OF THE INVENTION

The present invention relates to electroplating an electrically conductive material such as a relatively low resistive metal and especially copper onto a platable resistive metal barrier layer or stack of layers. More particularly, the present invention relates to an apparatus for directly plating onto the resistive metal without the need of a seed or catalyst layer, and especially without the need of a copper seed layer (even though a thin seed may be present, e.g. about 1.ANG.-about 10.ANG.). The present invention makes it possible to form a continuous and relatively uniform layer by growing a thin film from the edge of the surface to be plated towards its center by controlling the conditions of the current or voltage being applied.

BACKGROUND OF THE INVENTION

The current damascene plating process and especially that for copper requires a copper seed as a conductive layer on top of the highly resistive barrier liner which covers the underlying substrate such as a patterned wafer. The continuous miniaturization of ULSI technology will eventually require the elimination of this copper seed layer. Without this conductive seed, an applied current or voltage will drop off drastically within a short distance from the edge where the electrical contact is made (as will be described below.) As a result of this so-called terminal effect, a sufficient overpotential, η, for copper deposition will only exist near the edge of the substrate and plating is observed at the edge of the substrate only. When applied current is based on the total area of the substrate the effective current density for the perimeter ring is much higher and as a result burned, powdery deposits may be obtained.

Conventional methods to overcome the terminal effects for thin seed layers such as low plating current, segmented anode configuration, high copper concentration and low conductivity (low acid concentration) copper plating baths improve the current distribution and result in a more uniform film thickness. However, these methods apply only in the case where a sufficient plating overpotential exists over the whole substrate surface, from edge to center. For very thin seed layers and more importantly in the absence of a seed layer, the terminal effect of the resistive liner or seed causes such a drastic increase in the potential of the liner material, U_m(r), from the edge (r=r₀) to center (r=0) of the wafer, that the overpotential, η, becomes zero at a certain distance from the electrical contact and no further plating can occur:

η=U_eq,Cu²⁺_Cu−U_m(r) (1)

with U_eq,cu²⁺_/Cuthe equilibrium potential (Nernst potential) for copper deposition.

Copper deposition will proceed when η>0, i.e. when U_m(r)<U_eq,Cu²⁺_/Cu. In the case of thin copper seeds (5-50 nm), the sheet resistance is still low enough to ensure deposition over the whole substrate surface, although with a non-uniform growth rate in the case of a primary current distribution. In contrast, in the case of highly resistive liner, the drop-off in the overpotential is much more severe and becomes zero at a certain distance, x=r₀−r, from the edge of the wafer. In this case, deposition is only observed at the edge of the wafer. Additionally, too low current or overpotential results in a low density of nucleation sites leading to powdery, poorly adherent deposits.

As with copper, the principle of seedless plating holds for the deposition of any conductive material (metal, compound, alloy, composite, semi-metal or semiconductor) onto a resistive substrate.

SUMMARY OF THE INVENTION

The present invention provides an apparatus for electroplating a conductive material, such as copper, on a liner or substrate. The apparatus includes:

(a) at least one auxiliary electrode, wherein the at least one auxiliary electrode provides a counter electrode to the liner or substrate, wherein the liner or substrate acts as a first electrode;

(b) a programmable power supply providing for the generation of a current between the at least one auxiliary electrode and the liner or substrate, allowing for the conductive material to be electroplated onto the liner or substrate, and further providing for the adjustment of the current as a function of the change in the area of the conductive material as it is electroplated on the liner or substrate;

(c) a measuring device to detect the propagation of the front of the electroplated material over the surface of the liner or substrate; and

(d) a computer to process the output of the measuring device and calculate a new current to be applied by the programmable power supply as a function of the output of the measuring device.

The measuring device of the apparatus is not limited and can include one or more reference electrodes, a light source (such as a laser or light-emitting diode) and at least one photo detector (such as a photodiode) to measure the reflectivity of the at least one light source, an alternating current or voltage generator and analyzer (such as a frequency response analyzer (FRA) or Lock-in amplifier) to measure the electrochemical impedance of the system, and/or an alternating electromagnetic field generator and sensor for Eddy-current measurements.

The present invention further relates to methods of using the apparatus of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the present invention will become apparent upon consideration of the following detailed description of the invention when read in conjunction with the drawings, in which:

FIG. 1 shows the calculated change in overpotential, η, (calculated using the Bessel function assuming a linear change in current) for copper seeds (FIG. 1A) and platable liners (FIG. 1B) with different sheet resistance values as a function of distance from the center of a wafer;

FIG. 2A shows a set of conventional electronic components, which symbolically represents the path of current flow from an electrical contact with the wafer (cathode) to the opposite electrode (anode), for plating a certain spot on a wafer;

FIG. 2B shows the difference in resistive path for different spots on a wafer in a conventional cup or fountain plater;

FIG. 3 shows a schematic representation of the progressive growing of copper from the edge to the center of a wafer with an associated increase in current;

FIG. 4 shows a schematic representation of a basic two-electrode setup for direct plating on a wafer with a platable resistive metal layer stack in contact with the plating bath, using a programmable power supply controlling the current and voltage between the wafer (cathode) and an auxiliary electrode (anode);

FIG. 5 shows a schematic representation of an advanced setup for direct plating allowing the measurement of the advancement of the plated metal from edge to center, and feed-back to a computer to control the current and voltage accordingly;

FIG. 6 shows a schematic representation of a basic three-electrode setup for direct plating on a wafer with a platable resistive metal layer stack in contact with the plating bath, using a programmable power supply that can control the current between the wafer (cathode) and an auxiliary electrode (anode), and can measure and control the voltage between the wafer and the reference electrode;

FIG. 7 shows the plating potential between a rectangular strip (3 cm wide, 9 cm long) with a resistive TaN/Ru liner (with electrical contact made on one end of the 9 cm long strip) and a saturated mercury-mercury sulfate reference electrode during direct plating of copper (constant current of 0.123 A) for in-situ monitoring of the copper front progression;

FIG. 8 shows a schematic representation of a plating potential measurement using an array of reference electrodes (FIG. 8A), a reference electrode moving over the wafer surface (FIG. 8B), and an expected plating potential response (FIG. 8C);

FIG. 9A shows a schematic representation of an experimental setup used to demonstrate the concept of light reflectivity as means of measuring the advancement of a plated copper front;

FIG. 9B shows an example of the photo-voltage response during direct plating of copper on a resistive Ru layer;

FIG. 10 shows a schematic representation of a light reflectivity measurement using an array of LED's and photo diodes (FIG. 10A), a single set of LED and photo diode moving over a wafer surface (FIG. 10B), and an expected photo-voltage response (FIG. OC);

FIG. 11 shows the real and imaginary components of the measured electrochemical impedance, Z_realand Z_imag, during direct copper plating on a rectangular strip (3 cm wide, 9 cm long) with a resistive TaN/Ru liner stack (with electrical contact made on one end of the 9 cm long strip), illustrating the concept of AC impedance measurements for in-situ monitoring of the copper front progression (FIG. 11A shows the change Of Z_realand Z_imagwith time and FIG. 11B shows the variation of Z_realand Z_imagwith plated copper area according to one embodiment of the invention);

FIG. 12 shows a flow-chart representing a concept of the invention where the out-put signal of the measuring device is directly used for adjusting the current through a feed-back loop and for detection of the point of complete surface coverage; and

FIG. 13 shows a flow-chart representing a concept of the invention where the out-put signal of the measuring device is used for in-situ monitoring of the copper front progression and calculation and the current to be applied.

DETAILED DESCRIPTION OF THE INVENTION

U.S. Published Application No. 2004/0069648 A1, the entire disclosure of which is incorporated herein by reference, discloses a method for the direct electroplating of a relatively low resistive metal, such as copper, on a resistive substrate. That method allows plating of copper directly on at least one liner layer, where the liner layer(s) act as a diffusion barrier for copper into the dielectric. These diffusion barrier layers typically have a sheet resistance, R_s, which can be several orders of magnitude higher than for currently used copper seed layers. For example, a typical diffusion barrier layer sheet resistance may be in the range of 5 to 300Ω/square, whereas copper seed layers may have a resistance in the range of 1 to 3Ω/square.

The method disclosed in U.S. Published Application No. 2004/0069648 A1 can be described as direct plating or seedless plating. This method is based on the fundamental concept that the driving force for plating, known as the overpotential, η, becomes non-existent or nil at a certain distance from where electrical contact is made, the electrical terminal. For back-end processing of silicon wafers, electrical contact is typically made around the edge of a wafer, using multiple pins or a sealable ring contact. Accordingly, in such processing, as the distance from a wafer edge increases, the overpotential can be expected to decrease. In direct or seedless plating, this overpotential decrease generally occurs to a far greater extent than in conventional plating. This effect is the direct result of the severe potential drop (also known as IR-drop and terminal effect) in the resistive liner. FIG. 1 shows the calculated change in the overpotential (calculated using the Bessel function assuming a linear change in current) for copper seeds (FIG. 1a) and platable liners (FIG. 1b) with different sheet resistance values.

Even for very thin copper seeds, a plating overpotential exists in the center and edge of the wafer. However, the thinner the copper seed, the greater the expected potential drop from the edge to the center of the wafer. Such potential drop typically results in a strong non-uniform potential or current distribution over the wafer surface, but plating occurs everywhere at the wafer surface, even though at different rates. Many new plating stations have one or more hardware solutions to deal with the terminal effect and provide more uniform current distributions. All of these solutions basically provide different ways to compensate for the high resistance of the thin seed.

The path of the current flow from the electrical contacts with the wafer (cathode) to the opposite electrode (anode) in the plating cell can be represented by a set of electronic components, such as resistors and capacitors. FIG. 2a shows the equivalent circuit for plating a certain spot on a wafer and FIG. 2b shows the difference in resistive path for different spots on the wafer in a conventional cup or fountain plater. The capacitor shown in FIG. 2, which represents the double layer or so-called Helmholtz layer at the electrode/electrolyte interface, only plays a role during pulse plating or methods using alternating current (AC). By way of comparison, in direct current (DC) plating, only the resistors are of importance to understand the distribution of the current. In such case, the applied voltage is distributed as follows:

V_applied=η+I(R_substrate+R_solution) (2)

The difference in plating overpotential for a spot on the wafer close to the electrical terminal (current path 1 in FIG. 2b), and a spot closer to the wafer center (current path 2 in FIG. 2b), is the result of the additional large resistance of the substrate in the latter case. A higher substrate resistance can be expected to result in more challenging processing conditions with regard to both overpotential and current distribution. Notably, the current will be lower in a region closer to the center of the wafer (smaller overpotential), which slightly counteracts the drop in potential, which is also dependent on current.

One method of counteracting the effect of increased substrate resistance resides in making the solution resistance substantially high so that the change in substrate resistance has little or no effect on the potential drop, thereby allowing the overpotential to be essentially the same from edge to center. This concept forms the basis for one technique for uniform current distribution.

One method of increasing the solution resistance involves lowering its ionic strength or conductivity by using an electroplating bath with low acidity. In this regard, see, H. Deligianni et al. “Model of wafer thickness uniformity in an electroplating tool, Electrochemical Processing in ULSI Fabrication and Semiconductor/Metal Deposition II”, Proceedings of the International Symposium (Electrochemical Society Proceedings Vol. 99-9) 83-95 (1999), the entire disclosure of which is incorporated herein by reference. However, such a method may not be sufficient for very thin copper seeds and, in addition, such a method typically requires hardware modifications. Another method involves artificially increasing the solution resistance by using a plater that comprises a porous resistive element placed between a cathode and an anode. “EREX” from Ebara Corporation, is an example of a device that performs this method.

Other methods involve using segmented anodes to modify the current flow distribution In this regard, see, for example, U.S. Pat. No. 5,156,730 to Bhatt et al., U.S. Pat. No. 6,497,801 to Woodruff et al., U.S. Pat. No. 6,660,137 to Wilson et al., and U.S. Pat. No. 6,773,571 to Mayer et al., the entire disclosures of which are incorporated herein by reference. Even though these methods tend to be more complex, they also rely on the solution resistance where the path of least resistance is determined by the distance from the multiple anodes to different spots on the cathode, as well as the polarization of each anode.

Thieves may also be used to provide increased center to edge uniformity. In this regard, see S. Mehdizadeh et al., “Optimization of Electrodeposit Uniformity by the Use of Auxiliary Electrodes”, J. Electrochem. Soc., Vol. 137, No 1, p. 110-116, (January 1990), the entire disclosure of which is incorporated herein by reference.

In all of the above approaches, different kinds of hardware are used in an attempt to create uniform current distribution by correcting the change in overpotential along the surface. Notably, this approach assumes that the overpotential can be described by a continuous function. However, when the substrate resistance is large enough to cause the overpotential to drop to zero, the description of the overpotential along the wafer surface becomes discontinuous. In such case, correction of the effective series resistive by hardware becomes extremely difficult.

U.S. Published Application No. 2004/0069648 A1 provides a method for direct plating, which can overcome at least one of the challenges discussed above, including the situation where the overpotential along the wafer surface can be described as discontinuous. The method disclosed therein imparts a technique for plating across a wafer, having a thin liner only, from the edge towards the center; i.e the wafer coverage is not instantaneous as with conventional techniques but changes with time. This method applies a current waveform, which accounts for the change in plated copper area and is illustrated schematically in FIG. 3. The operating principle of this method involves applying a continuous current or voltage ramp (or multiple current or voltage steps approaching continuous change) to keep the effective local current density constant within a certain range. When the effective local current density needs to be controlled accurately, a polynomial function for the current can be applied, which can be determined by measuring the progression rate of the plated front from the edge to the center ex-situ.

The present invention relates to an apparatus that can perform the method disclosed in U.S. Published Application No. 2004/0069648 A1. Specifically, the present invention relates to an apparatus for direct plating on resistive liners having an integrated in-situ measuring system to follow the actual progress of a plated front during plating. Feed-back of this information to the power supply allows for more precise control of the current waveform to provide a constant local effective current density during plating of the trench and via features.

The present invention is not limited to any specific type of plating apparatus, and includes, for example, cup and/or fountain platers (“Equinox” from Semitool and “Sabre” from Novellus), thin cell platers (“Slim cell” from AMAT and “EREX” from Ebara) and paddle cells (IBM). In addition, the present invention relates to plater configurations independent of cell volume, anode configurations (such as separated anodes or virtual anodes), diffusers for current distribution (resistive and not resistive), thiefs, flow, rotation, and/or solution chemistry.

The current densities necessary to achieve plating in an apparatus corresponding to the invention are not limited and can cover a very broad range. The current densities may, for example, range from about 10 μA/cm²to about 2 A/cm², depending on the application, the plating process, the plated material and the metal ion concentration in the plating bath. The current densities may typically be expected to range from about 0.1 mA/cm²to about 100 mA/cm², such as from about 3 mA/cm to about 60 mA/cm². The voltage depends on the tool configuration. While not limited, the voltage employed typically ranges from about 0 to about 50 volts, such as from about 0 to about 20 volts, or from about 0 to about 10 volts.

The solution chemistry of the plating bath is not limited and includes all plating bath materials disclosed in U.S. Published Application No. 2004/0069648 A1. For example, the plating bath may comprise a copper salt, optionally containing a mineral acid, and optionally one or more additives selected from the group consisting of an inorganic halide salt, an organic sulfur compound with water solubilizing groups, a bath-soluble oxygen-containing compound, a bath-soluble polyether compound, or a bath-soluble organic nitrogen compound that may also contain at least one sulfur atom.

While copper is the primary conductive material contemplated for deposition, an apparatus falling within the scope of the present invention can be used to plate other materials. Examples include all platable metals, alloys, composites, semiconductors and/or polymers from aqueous, non-aqueous or mixed electrolyte solutions or melts. Metals that can be plated according to processes falling within the scope of the present invention may include, for example, those selected from the group consisting of Cu, Ag, Au, Pb, Ni, Pd, Co, Pt, Rh, Ru, Cr, Sb, Bi, Sn, In, Fe, Zn, Cd and and alloys, mixtures, and multilayers of the same. Other metals that may be plated can include, for example, those selected from the group consisting of Re, Tc, Os, Ir, Se, Te, Mn, and alloys, mixtures, and multilayers of the same, as well as alloys, mixtures and multilayers of any of the above metals with Al, Mg, W, V, Ti, Ta, Mo, Ce, Ga, Gd, Hf, Zr, La, Y, Sr, Tl, Eu, Dy, Ho and Nb. In addition, oxides, sulfides, phosfites, and borides, of any of the above metals may be used, as well as any alloys mixtures or multilayers of any of the above materials with Si, C, Ge, As, O, P, S, and/or B.

Metals that may be plated further include elemental semiconductors such as Si and Ge, which may further include C, H and/or F, and alloys, mixtures, and multilayers of the same. In addition, materials that may be plated include: semiconducting oxides, such as ZnO and TiO₂; III-V semiconductors such as InAs, InP, InSb and GaS; II-VI semiconductors such as CdSe, CdS, CdTe, ZnS, ZnSe, ZnTe; and tertiary and quaternary semiconductor compounds of combinations above and with Cu, Sr, Ba, and alloys, mixtures, and multilayers of the same. In addition, materials that may be plated include: conducting oxides wherein the metal is selected from the group consisting of Cd, Sn, Ga, In, Cu, Ru, Re, and Pb, and alloys, mixtures, and multilayers of the same; conducting polymers, for example, polypyrrole and polyaniline; semiconducting polymers; and biominerals.

The thickness of the plated metal, while not limited, can typically be expected to range from about 0.02 microns to about 25 microns, such as from about 0.1 microns to about 2 microns, including from about 0.3 microns to about 1 micron.

A plating apparatus falling within the scope of the present invention may be used in the fabrication of semiconductor wafers, such as Si or Ge, with diameters ranging from, for example, about 5 inches (about 120 mm) to about 12 inches (about 300 mm). The apparatus may also be used for substrates with other than circular geometries. In U.S. Published Application No. 2004/0069648 A1, an example was given for a rectangular shaped substrate with electrical contact made on one edge. In such case, the plated front migrates from the edge, where contact was made, towards the opposite edge over time. In such case, in-situ measurement of the copper front position is also desirable.

The liner or diffusion barrier layer or layers on which the conductive metal, such as copper, may be plated is not limited. Examples of materials that can be used include tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, ruthenium, platinum, rhodium, palladium, rhenium, cobalt, molybdenum, iridium, vanadium, chromium, yttrium, zirconium, niobium, hafnium and mixtures, alloys and multilayers thereof. Further examples include gold, thallium, lead, bismuth, iron, nickel, copper, aluminum, silicon, carbon, germanium, gallium, arsenic, selenium, rubidium, strontium, silver, cadmium, tin, antimony, tellurium, osmium, and mixtures, alloys, and multilayers thereof. The alloys of the above metals can include various alloying materials including, but not limited, to O, S, N, B and P.

A basic configuration of an apparatus relating to the invention is presented schematically in FIG. 2. This figure shows a resistive substrate, such as a silicon wafer with a thin copper barrier liner, incorporated in a standard plating apparatus such as a cup or fountain plater (FIG. 2b). The resistive substrate is contacted with an electrical contact, such as a ring contacting the liner at the edge of the wafer, and connected to the negative terminal of a programmable power supply. An anode (consumable or inert) is connected to the positive terminal of the power supply. The desired current waveform can be inputted through a computer controlling the power supply.

FIG. 4 can also be interpreted as showing a basic configuration of an apparatus relating to the invention. This figure shows a silicon wafer with a resistive substrate 10, an anode 20, a plating bath 30, and a programmable power supply 40. Without the use of a detection method to measure the progression rate of a plated front, the progression rate of a plated front would be expected to be determined ex-situ, for example, by partial plating experiments.

A representation of an example of a device having an integrated in-situ measuring system to follow the actual progress of a plated front is illustrated schematically in FIG. 5. This figure shows a resistive substrate 10, an anode 20, and a plating bath 30. An in-situ measuring device 60 is used to determine the area of a plated material 50, such as copper. This information is then used in a feed-back loop via a computer 70 to control the power supply 40. In such a device, relatively precise current control can be achieved and the effective local current density for plating each feature at the wafer can be approximately uniform.

In devices falling within the scope of the present invention, the in-situ measurement of the plated copper front is not limited to any particular method. Examples of methods that can be used include: potential measurement, optical measurement, AC or impedance measurement, and Eddy current measurement.

Potential Measurement

The potential measurement method is based on the principle that the plating potential will change when the plated copper increases and will reach a certain value when the whole wafer is covered. Measurement of this potential provides an indirect method for controlling the applied current waveform. The potential can be measured between the cathode and anode, for example, as shown in the configuration of FIG. 4. However, in this configuration, the measured potential difference is the result of both the electrode potential at the cathode/electrolyte interface and the anode/electrolyte interface together with tooling factors such as distance between anode and cathode, diffusers, ionic strength of the plating solution, and contact resistance. In this case, no distinction can be made between changes occurring at the anode and cathode. A more reliable method is to use at least one reference electrode, which has a constant electrode potential. The potential is measured between the work piece or wafer (cathode) and the reference electrode. In this case, the measured potential difference or plating potential is unaffected by changes at the anode.

FIG. 6, schematically represents a plating tool in which a reference electrode 80 is placed in the plating bath 30 in-between the wafer with resistive liner 20 and anode 10. For potential control, a three or four terminal power supply 41 is now required, where one of the additional inputs can be used for connecting the reference electrode 80. Examples of reference electrodes include: Calomel, mercury sulfate, silver and/or silver/silver chloride. A pseudo reference can also be used as a third electrode. Examples of pseudo reference electrodes include: copper, platinum, or gold wire. Typical electrode potentials for some reference electrodes are 0.24V for Saturated calomel electrode (SCE), 0.22V for Ag/AgCl electrode and 0.65V for saturated mercury-mercury sulfate electrode (SMSE). By convention the “Normal hydrogen electrode” (NHE) also called “Standard hydrogen electrode” (SHE) has an electrode potential of 0V (and is the potential of 1 mole/liter of protons, H⁺, in chemical equilibrium with hydrogen gas, H₂, at 1 atmosphere).

The plating potential (measured potential difference between work piece and reference) is the sum of the electrode potential difference, U, and the IR-drop in the solution (plating potential=U+IR). The electrode potential difference depends on the electrode potential of the reference (see stated values above). A typical range of electrode potential differences, U, for copper plating is about 0.34V to −1V versus NHE; 0.1V to −0.76V versus SCE, or −0.31V to −1.65V versus SMSE. The IR-drop depends on the applied current, solution resistance and the position of the reference electrode in the plating cell. Values may range from 0 to 12V. The IR-drop is the result of the electric field between the anode and cathode, and can be minimized by bringing the reference electrode as close as possible to the substrate surface. In practice, this can be done with a Luggin capillary. A Luggin capillary, is a thin capillary brought close to the work piece (wafer surface in our case), to sample the potential of the working electrode/electrolyte interface without interference of the electric field present between the cathode and anode in the solution.

The electrode potential of a work piece is typically dependent on changes in the chemical composition of the surface (deposition of foreign material or adsorption of organic molecules) and changes in electrolyte composition (e.g. concentration changes due to ion depletion) at the measured interface. Thus, in the case of direct copper plating on a liner, such as ruthenium, by sequential surface coverage according to the teachings of application Ser. No. 10/269,956, the transformation of a bare Ru surface towards a complete Cu surface, with in-between the co-existence of Cu and Ru with changing ratio in surface coverage, is directly measurable by the change in plating potential.

In this regard, see FIG. 7A, which shows the response of the plating potential during direct copper plating on a narrow Ru strip (3 cm wide, 9 cm long silicon/SiO₂strip with TaN/Ru liner, submersed in a copper plating bath). Electrical contact was made on one end of the strip, allowing copper growth along the 9 cm strip towards the other end. The current was kept constant at 0.123A (Pt mesh counter electrode, and saturated mercury-mercury sulfate reference electrode). The plating potential (U+IR) is about −7V for about 10 seconds and then drops rapidly to −7.5V at about 50 s and remained constant thereafter. The Ru surface gets fully covered with Cu in about 50 seconds (the progression of the copper front could be observed visually in the glass cell as well). From this, a constant copper front progression rate of 0.18 cm/second can be estimated. The change in area is 0.54 cm²/second.

FIG. 7B shows the plating potential as a function of plated Cu area, which could be used as a calibration curve according to the invention. In one embodiment of this invention, the plating potential is used for in-situ monitoring of the plated copper front and exact control of the current program. This method requires a calibration curve which is used by the computer for calculating the current based on the plating potential output. The calibration curve needs to be determined in advance by correlation of plating potential with a more direct measurement of the copper front. This can be done by a combination of other in-situ monitoring techniques, such as optical measurements as described below, or by ex-situ measurements such as sheet-resistance (Rs) mapping, ellipsometry, chemical analysis, reflectivity, etc. In the latter case, partial plating experiments allow correlation between different positions along the plating potential-time curve with experimentally measured copper areas. Note that the approach described above has limitations since the plating potential is an indirect measure of the plated copper area, and thus a more direct approach is desirable.

Since the wafer coverage changes over time, the electric field between the cathode and anode changes over time. The change in electrical field can be measured as changes in the plating potential (through change in the IR-drop) with several reference electrodes positioned at different locations along the wafer radius. Alternatively, at least one fast moving reference electrode along the wafer radius can be used. The plating potential measured by at reference electrodes near copper covered area will be drastically different from those measured near bare liner areas, thus creating a diameter scan or profile of the copper coverage. In one embodiment of this invention, an array of reference electrodes in placed along the wafer radius, and as many volt meters are used to measure the local plating potential. In another embodiment, at least one reference electrode is moving fast over the wafer surface from edge to center, to measure the plating potential profile over time.

In this regard, see FIG. 8 showing a schematic illustration of an array of reference electrodes 100 (FIG. 8A) and a fast moving reference electrode 110 (FIG. 8B) across a partially plated wafer (wafer with resistive liner 10 and plated metal 50), and the expected potential response (FIG. 8C). The plating potential versus wafer radius information provides direct information of the plated metal area and thus allows exact control of the current by feed-back from the computer to the power supply.

In yet another embodiment, the reference electrode may follow the plated copper front (which is determined by the change-over in plating potential associated with change from liner, such as Ru, to plated metal, such as copper). The position of the reference electrode is a direct measure of the plated copper area.

Optical Measurement

When the reflectivity of the substrate and the plated copper is sufficiently different, light reflection measurements can be used to follow the plated copper front. An application of this principle is schematically represented in FIG. 9. FIG. 9A shows a diagram of a reflectivity measuring setup. In this figure, a wafer 10 is placed on a wafer chip rotator 20. A laser 30 provides a laser beam 40, which, with the help of mirrors 50, monitors the center for the wafer. The reflected beam 60 is collected at a photo-diode detector 70. A change in photo-voltage from the detector indicates the copper has reached the spot of light aimed at the surface. When a thick film is formed with good reflectivity, the reflectivity becomes essentially constant. Similar optical methods have been proposed for to monitor the removal rate of a metallization during CMP, see, for example, U.S. Pat. No. 6,707,540 to Lehman et al., the entire disclosure of which is incorporated herein by reference.

FIG. 9B shows the results of a simple experiment using a single spot in the center of a wafer according to the setup in FIG. 9A. In this experiment, a wafer piece measuring 4 centimeters by 4 centimeters and a copper plating bath was used and a constant current of about 80 mA was applied. As shown in FIG. 9B, the photo-voltage increased drastically when the copper reached the center of the wafer piece.

In an actual plating tool, several spots at the wafer may be illuminated through the use of several small light emitting devices (LED's) with the reflectivity monitored with a photo diode array. Alternatively, as for the plating potential method, at least one set of a LED and photo diode can be used, which is scanned rapidly over the wafer surface to measure the reflectivity as a function of wafer radius or track the copper front by positioning itself where the reflectivity difference is the largest (border between bare substrate, such as ruthenium liner, and plated metal, such as copper).

In this regard, see FIG. 10, showing a schematic illustration of an array of LED and photo diodes 120 (FIG. 10A) and a one set of fast moving LED and photo diode 130 (FIG. 10B) across a partially plated wafer (wafer with resistive liner 10 and plated metal 50), and the expected photo voltage or reflectivity (FIG. 10C). The reflectivity versus wafer radius information provides direct information of the plated metal area and thus allows exact control of the current by feed-back from the computer to the power supply.

In another embodiment, the reflectivity of the total substrate area can be measured, with current adjustments made as a function of this measurement. In this case the total measured reflectivity is a linear function of metal coverage and thus plated area, and the current is directly proportional with the measured reflectivity. For example in the case of direct copper plating on Ru, the reflectivity of Cu is higher than the Ru substrate. The maximum change in reflectivity (100%) corresponds to the difference in photo-voltage of a complete Cu surface, U_photo,Cu, and a complete Ru surface, U_photo,Ru. The total reflectivity, R(%), of a surface can be defined as:

R(%)=100×[V_photo,t−(V_photo,Cu−V_photo,Ru)]/(V_photo,Cu−V_photo,Ru),

with V_photo,tthe photo-voltage measured at time, t. When the reflectivity is proportional to the plated copper area, then the current is directly controlled by the determined reflectivity.

In the case of direct copper plating for back-end of line semiconductor processing, the semiconductor wafer itself can be used as photo-detector (since semiconductors form the bases of photo-diodes). The back of the wafer can be connected to a voltmeter, which is in communication with a computer to control the power supply.

In addition, other optical techniques such as light absorption, light scattering, or light emission (if the structure has light emitting properties) can be similarly used

AC Measurement

Another method of monitoring a plated metal front in an apparatus falling within the scope of the present invention involves AC or impedance measurements by superposition of a small alternating current or voltage to the applied current or voltage for plating by use of a sinusoidal signal generator. Such alternating voltage or current generates a respective alternating current or voltage response determined by the electrochemical impedance of the substrate/electrolyte interface. The electrochemical impedance can be measured using a Lock-in amplifier or Frequency response analyzer (FRA) by comparing the input and output sinusoidal signals which differ in amplitude and phase. The impedance vector (defined by its magnitude, /Z/ and phase angle, φ) can be represented by its real part, Z_real(representing the resistance of the interface) and an imaginary part, Z_imag(representing the capacitance of the interface). The measured electrochemical impedance depends strongly on the frequency of the applied sinusoidal signal. At very high frequencies (1 MHz-100 kHz), the series resistance of the system (electrical connections, wires, contact resistance and solution resistance) is measured (typically between 1 to 1000 ohms, depending on tool design and setup). The series resistance contains no information of the substrate/electrolyte interface and is therefore not suitable for this application. At very low frequencies (100 Hz-1 Hz), diffusion processes may determine the measured impedance (known in the art as the Warburg impedance), which is also independent of substrate and therefore not suitable for our application. In the intermediate frequency range (10 kHz-100 Hz), both the capacitance of the substrate/electrolyte double layer (known as the Helmholtz layer in the art, see FIG. 2A), and the resistance associated with the charge transfer over the electrode/electrolyte interface (R_ct, as in FIG. 2A) determine the measured impedance.

The electrochemical impedance for the bare substrate/electrolyte interface will be different than that for the interface of the electrolyte with a plated metal such as copper. Values can, for example, range from about 0.1 ohm cm²to about 1000 ohm cm²for the resistance and about 10 μFarad/cm²to about 100 μFarad/cm², depending on applied current and potential. Since the impedance depends on the surface area, the total measured impedance will be a function of the plated copper area. As with other methods described elsewhere herein, such measurements can be used in a closed loop to control the current program applied.

In this regard, see FIG. 1I A, which shows an example of the real and imaginary part of the impedance, measured in-situ during direct plating on a long silicon strip with a resistive Ru film on top (3 cm wide, 9 cm long strip with a resistive TaN/Ru liner stack and electrical contact made on one end of the 9 cm long strip, constant applied current of 0.135 A). The real part of the impedance, Zeal, increases linearly with time and reaches a somewhat constant value around 50 seconds, coinciding with the point of complete copper coverage. The imaginary part of the impedance, Z_imag, is constant up to about 35 seconds and then changes rapidly to reach a plateau again around 50 seconds. Since the copper area increases with time (linearly for a rectangular strip), and since, in this experiment, the current was kept constant, the current density decreased linearly with time.

Z_realand Z_imagare plotted as a function of plated Cu area in FIG. 11B. The change in Z_realis a direct measurement of the change in current density (Z_realis inversely proportional with current density). Hence, it is clear to a person in the art, that Z_realcan be used to directly monitor and control the current density at Cu. For example, in this case, keeping Z_realconstant by adjusting the current through a feed back loop is one way to control the current density with impedance measurements.

A flow diagram for a feed-back loop working according to these principles, is shown in the fist part of FIG. 13. In addition, Z_imagcan be used for controlling full coverage of the wafer or sample. The sharp change in Z_imagindicates the Cu coverage is coming to completion, and can be used as end-point detection. From that point on, conventional plating steps can be applied. The end of feed-back loop control is also incorporated in the flow chart of FIG. 13.

An embodiment for controlling the current density during wafer coverage step, using impedance measurement method is shown in FIG. 13. An initial constant current or voltage may be applied for a certain time to grow a copper ring around the edge. During or at the end of this time the impedance (Z) is measured. The subsequent applied currents, I(t) and/or voltage, V(t), are controlled by a feed-back loop and change with time in order to keep the real part of the impedance, Z_real, constant (dZ_real/dt=0); i.e. equal to the initially measured value. This feed-back loop is maintained until a drastic change in the imaginary part of the impedance is observed (dZ_imag/dt>>0). After this step, the wafer is completely covered with a continuous copper film, and conventional plating steps may be applied for then. For example, from that point on the current may be kept constant for a certain time to allow the copper thickness to grow, and small damascene features to fill.

Eddy Current

A somewhat analogous method to the AC measurement method involves the measurement of Eddy currents. Eddy currents are small currents near the surface of a wafer or substrate that exist as the result of an applied alternating magnetic field. Eddy currents are a function of the frequency and the magnetic flux as well as the resistivity and permeability of the surface. Since the surface gradually changes during plating, measured Eddy currents can be used to determine the plated copper area. As with other methods described elsewhere herein, such measurements can be used in a closed loop to control the current program applied. Eddy-current measurement methods are well known in the art of chemical mechanical polishing (CMP) and are typically used for end-point detection. In this regard, see for example, U.S. Pat. No. 6,072,313 to Li, et al. and U.S. Pat. No. 6,707,540 to Lehman, et al., the entire disclosures of which are incorporated herein by reference. In addition, see U.S. Pat. No. 4,556,845 to Strope, et al., the entire disclosure of which is incorporated herein by reference, which describes Eddy-current measurements for in-situ thickness evolution of an electroless deposit (i.e. formed without applied current or voltage).

Each of these methods is based on the measurement by a sensor of a current (Eddy current) induced in the film by an alternating electromagnetic field, and the sensor signal is dependent on the film thickness. Similar approaches can be used for monitoring the plated metal front. Similar to the reference electrode arrays and photodiode arrays used for the potential and optical methods, an array of coils for inducing an alternating magnetic field and Eddy current measurement can be used. Alternatively, a set of coils for Eddy-current measurements can be moved over the diameter of the surface to measure the thickness variation (with respect of before plating) for determination of the plated metal front.

FIG. 13 shows a schematic and flow-diagram for an embodiment using methods which measure the time dependent copper coverage, such as the potential method, the optical method and the Eddy current method. An input signal (such as a light beam) may be applied by the measuring instrument, which induces an output signal (such as a reflected light beam) measured by the measuring instrument. Alternatively, no external input signal is required, but an output signal (such as plating potential) is still measured. The output signal is a measure for the plated copper area, which is calculated by the computer. For this computation, a calibration curve may be required. The computer calculates the current according to the determined plated area (Current (I)=Area (A)×current density (i)), and communicates this current to the power supply. This process continues until full wafer coverage is achieved. At this point, the current program can continue using conventional plating steps.

While the present invention has been described in an illustrative manner, it should be understood that the terminology used is intended to be in a nature of words or description rather than of limitation. Furthermore, while the present invention has been described in terms of several illustrative embodiments, it is to be appreciated that those skilled in the art will readily apply these teachings to other possible variations of the inventions.

Apparatus for direct plating on resistive liners

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