The present disclosure relates to semiconductor assembly, and in particular, to an architecture and packaging for integrated circuits.
A high demand for semiconductors and their lack of supply has caused a shortage crisis that has impacted a variety of industries. The sourcing of dies from limited foundries is one of the issues that the industry is trying to solve. Adding to that, other critical components, such as redistribution layer (RDL) fanouts, organic substrates, and packaging assemblies that are necessary to build integrated circuits (e.g., application-specific integrated circuits (ASICs)), are also in short supply.
An apparatus is provided that includes a thin-film interconnect structure that comprises one or more polymeric layers and conductive plating, a first surface of the thin-film interconnect structure being configured to receive one or more dies, and a second surface of the thin-film interconnect structure being configured to receive a substrate. A method of assembling the apparatus into an integrated circuit assembly is also provided.
A redistribution layer (RDL) is an extra metal layer on an integrated circuit that makes the integrated circuit's input/output (TO) pads available at other locations of the chip, for better access to the pads where necessary. An RDL, also referred to as a RDL fanout or interconnect layer, is disposed between the substrate and the die, and is therefore a key element in integrated circuit packaging. Conventionally, the fabrication of RDL fanouts is controlled by the same foundries that also control the die technology and other processes. Additionally, due to the nature of conventional integrated circuit fabrication techniques, RDLs are fabricated on-site at the foundries. Therefore, original equipment manufacturers (OEMs) are highly dependent on these foundries, which limits the available alternative solutions.
In addition, driven by increased density and speed on network processing units (NPUs), graphics processing units (GPUs), artificial intelligence (AI)/machine learning (ML) chips, and ASICs, substrate layer count and size are increasing significantly, which results in the substrate being a significant cost of a chip (sequential build up, longer cycle time, and lower yield). This trend has led to an industry-wide shortage on substrates, and this trend is predicted to increase in the coming years.
Other issues in the current semiconductor architecture include a substantial increase in the number of layers in organic substrates, increasing the price and limiting the number of substrate fabrication houses capable of producing the substrates. Additionally, organic substrate body size has increased due to the number of dies needed, also increasing costs while limiting the number of substrates that can be brought to market. Organic substrates with a high number of layers and/or large body sizes can suffer reliability issues such as warpage, cracking solders, and the like.
Furthermore, assembling large integrated circuits with traditional printed circuit boards (PCBs) can lead to solder reliability issues due to reflow and warpage. For example, application-specific integrated circuit (ASIC) host board design complexity has increased due to routing of high number of IOs and voltage rails, causing both signal integrity and power integrity limitations. In ASIC via fields, it is extremely difficult to route differential channels, thus limiting manufacturers to single-ended topologies due to their immunity issues. A large number of anti-pads for limiting the copper density increases the number of power shapes to compensate for the routing topologies.
With the advent of complex chip architectures such as co-packaged optics (CPOs), Near Package Optics (NPOs), a silicon photonic packaging (SPO), and other next generation optical tiles/modules, there is a desire to control the design, optimization of fabrication processes, and manufacturing of different building blocks using different strategies to reduce the overall cost, to align with OEM resiliency business plans, and to incorporate the latest technologies and processes.
Accordingly, present embodiments provide an alternative solution to a redistribution layer by providing a thin-film interconnect structure that includes multiple polymeric layers that are plated with conductive material (e.g., copper) where appropriate, to achieve any desirable fine pitch geometry for fanout-style redistribution of IOs. The thin-film interconnect structure benefits from the finer pitch geometries that are achievable using thin-film techniques. Additionally, by using a thin-film approach, present embodiments enable an interconnect structure to be fabricated in a larger panel size (e.g., larger than 300 mm wafer), off-site from the foundry that fabricates the integrated circuit. Thus, supply-chain restrictions are avoided, as the interconnect structure can be fabricated off-site and then provided in between the dies and the substrate when an integrated circuit is assembled.
Moreover, thin-film polymeric layers enable many components, such as capacitors or power management elements, to be provided in the interconnect structure rather than the substrate. Thus, present embodiments offer improvements to integrated circuits by reducing the number of the substrate layers. Accordingly, present embodiments enable the benefit of stand-alone fabrication of an interconnect structure by avoiding the conventional silicon-wafer approach, while also achieving better electrical performance compared to standard complex substrates. The improvements disclosed herein are not limited to ASICs, but can benefit any semiconductor architecture. For example, these techniques can be used in a CPO, an NPO, a central processing unit (CPU), a graphical processing unit (GPU), a network processing unit (NPU), and other next-generation semiconductor architectures
With reference made to
As depicted, integrated circuit package 100 includes a plurality of dies 110, a moulding compound 115, a wafer redistribution layer (wRDL) 120, and a substrate 130. Typically, a packaging assembly house assembles all of these components together. In general, substrate 130 is an organic epoxy-based sequential build-up substrate (e.g., fabricated one layer at a time) or ceramic based co-fired substrate. The moulding compound 115 can include a glass-fiber reinforced thermoset polymer material or other suitable moulding material. Even with advances in fabrication processes, the technologies and the materials of substrates still suffer from many limitations. With the use of a large body substrate, e.g., for a CPO, not many fabrication substrate houses can fabricate substrate sizes that exceed a 110 mm by 110 mm threshold with 9/2/9 layers. With very limited understanding of what fabrication yields will be, costs are driven up. Additionally, there are limited suppliers from which to choose. In addition to uncertainties around volume production readiness, quality and reliability criteria impose supply base constraints that are hard to overcome.
Moreover, on the performance side, combining the high insertion loss or dissipation factor (Df) of the materials (when compared to ultra-low loss for PCB) and the high copper surface roughness (compared to, for example, the smoothness of PCB hyper very low profile (HVLP) copper foil) the losses of the traces tend to be high, increasing the power consumption due to the many taps for equalizing and compensating the induced and intrinsic losses and inter-symbol interference impairments. With conventional substrates, the losses in the substrate exceed 4 dB, even with the use of the latest dielectric materials.
Still referring to
To solve many manufacturability and multi-vendor constraints, an ASIC according to one or more embodiments presented herein comprises building blocks that can be manufactured by different suppliers, allowing blocks from different suppliers to be assembled.
Now with reference to
At the first phase 210, a wafer 240 and molded wafer 250 are molded to provide one or more dies (e.g., die 215). At the second phase 220, wRDL 225 is fabricated on the molded wafer (e.g., molded wafer 250 of phase 210) thereby providing die 215. Accordingly, due to the constraints of conventional fabrication techniques, wRDL 225 must be assembled at the same location (fabrication facility) that die 215 is fabricated.
At the third phase 230, the die 215 and wRDL 225 assembly is soldered to substrate 235, which may be an organic build-up substrate or other substrate. Thus, phases 210-230 depict a conventional technique for fabricating integrated circuit packages in a die-first manner.
Now, present embodiments shall be described, beginning with reference to
At phase 302, an interconnect structure 310 is fabricated. Interconnect structure 310 may be a thin-film interconnect structure that is composed of multiple polymeric thin-film layers, among which a conductive material (e.g., copper) is selectively provided to achieve a desired geometry for redistributing one or more IOs (e.g., in a fanout manner). Interconnect structure 310 is fabricated independently of a die, and therefore interconnect structure 310 need not be fabricated at a same facility that fabricates a die and/or substrate. The fabrication of interconnect structure 310 is depicted and described in further detail with reference to
At phase 304, interconnect structure 310 is bonded to a substrate (e.g., substrate 320). The substrate may include an organic build-up substrate or other substrate. Substrate 320 is used as a base material in semiconductor applications and manufacturing. Unlike inorganic substrates, an organic substrate may be made of organic small molecules or polymers, including polycyclic aromatic compounds such as pentacene, anthracene, and rubrene.
At phase 306, a die wafer 325 is diced to individual dies (e.g., die 330). Next, die 330 is bonded to the top surface of interconnect structure 310 (e.g., the surface opposite from the surface to which substrate 320 is bonded). Accordingly, interconnect structure 310 is provided between die 330 and substrate 320 to enable redistribution of IOs, as well as other features in accordance with present embodiments. Die 330, interconnect structure 310, and substrate 320 together form assembly 340, which is an integrated circuit package. The integrated circuit may be any desired circuit, such as an ASIC, CPU, GPU, NPU, CPO, NPO, SPO, and the like.
With reference now to
Initially, a layer 420 of thin-film polymeric material is provided to a ridge carrier 410 at phase 402. Layer 420 is a thin layer of polymeric material that is coated onto ridge carrier 410 in a large panel form. This dielectric polymeric layer is then laser-drilled, plated with a conductive material 430 (e.g., copper, silver, etc.), and patterned using a lithography tool.
At phase 404, one or more additional layers 420 are provided, one layer at a time, in a build-up manner, with each layer similarly being laser-drilled, plated with conductive material 430, and patterned to achieve a desired geometry. Once completed, this interconnect structure may be transferred to another facility (e.g., a substrate fabrication or Printed Circuit Board (PCB) facility that will complete fabrication of an integrated circuit substrate or PCB).
Once the interconnect structure is completed, the interconnect structure is provided to a substrate (e.g., substrate 320 or PCB) at phase 406. The interconnect structure is inverted when bonded to substrate 320, so that the top-most layer (e.g., the last layer to be deposited) contacts the surface of substrate 320. Additionally, ridge carrier 410 is removed. A top layer metallization 440 is provided for chip attachment. Upon completion of phase 406, dies may be added to the top surface of the interconnect structure and the integrated circuit package can be completed.
With reference now to
Interconnect structure 600 can be built using up to five layers or more. Since interconnect structure 600 is a standalone block, interconnect structure 600 can be tested before bonding to a substrate or PCB to improve the overall yield before the next integration step. Interconnect structure 600 can be finished by adding micro-pads 610, which may be attached onto dies with micro-solder bumps and/or copper pillar bumps. Micro-pads 610 may have a pitch that ranges between, e.g., 10 μm-40 μm. Additionally, passive components, such as capacitors and/or power management elements can be integrated into the layers 630 of interconnect structure 600.
The flatness and coefficient of linear thermal expansion (CTE) of interconnect structure 600 can match traditional RDLs. Another capability of interconnect structure 600 is an increase in the body size, if desired, which can exceed 300 mm×300 mm, leveraging a standard panel size of 21 inches by 24 inches. In contrast, conventional RDLs are limited to 300 mm wafer lithography process. Additionally, the signal integrity of interconnect structure 600 may be improved as compared to conventional RDLs.
Notably, interconnect structure 600 can be designed with integrated circuit packaging tools following fewer rules and policies. This enables an OEM to develop new technologies. The properties of the geometries for the channels, and via transitions for both data and power may be set based on the desired operation of the integrated circuit. Accordingly, interconnect structure 600 can serve as a common fanout interface for all future complex chip platforms such as CPOs, NPOs, or other ASICs.
The top of substrate 700 can support an interconnect structure 705, as shown in
The assembly 730 of
At phase 904, interconnect structure 910 is bonded to substrate 920, which can include a build-up substrate, a bismaleimide triazine substrate, a PCB substrate, etc. By providing capacitors as internal components 940, the need for surface capacitors on substrate 920 is eliminated.
At phase 906, a die 930 is soldered to interconnect structure 910 to provide a completed integrated circuit package. By providing power management dies as internal components 940, many issues related to power distribution and power integrity can be addressed, thereby improving the performance of the integrated circuit.
The first option for block 1000 includes the use of a substrate-like building block. The substrate-like building block uses the same architecture/design/tools as the CPO substrate-like building block. One difference is that the addition of power layers and increase in the size of the block allow for the addition of the voltage regulator modules (VRMs) and other components as mentioned above. Since these substrate-like blocks are based on a panel that may be 21 inches by 24 inches, the substrate-like block can be as large as desired. Generally, the limitations are due to the equipment used for imaging the patterns in addition to manufacturing yields due to the fine Geometries used.
A second option for block 1000 includes the use of a PCB-like building block. First, PCB-like technologies use HDI techniques and processes in advanced PCB laminates. This allows the use of dielectric materials in the PCB, including ultra-low loss materials. In addition, using advanced technologies for copper treatments and processes in the PCB reduces the surface roughness which in turn reduces the losses at high frequencies.
Both options can support building fine pad pitches as low as 0.3 mm. However, the equipment used to build the PCB-like layers and geometries may be limited in terms of how fine the geometries can be with a minimum linewidth and spacing around, e.g., 4 μm or less. Meanwhile, a substrate-like linewidth and spacing minimum may be about 14-15 μm. These are useful for reducing long channel losses that favor PCB-like building blocks compared to substrate-like building blocks in addition to the capability of adding many power layers compared to substrate-like blocks. Both options can be used to build an NPO based on a desired power copper density and channel losses. The next step is the assembly of optical tiles that follow the same process as in CPOs.
Now with reference to
Accordingly, a flexible semiconductor architecture based on building blocks that disaggregates the fully integrated flow used in current chip assembly is disclosed. This results in a more parallel and resilient approach that will allow manufacturers to build any chip that aligns not only with cost reduction but also with improved performance in term of signal integrity and power reduction.
A thin-film interconnect structure is fabricated at operation 1210. The interconnect structure may be composed of several layers of a polymeric thin-film material that is deposited layer-by-layer onto a ridge carrier. After each layer is deposited, laser drilling may be conducted and a conductive plating (e.g., copper) may be provided where desired in order to achieve a particular geometry. The thin-film interconnect structure may be obtained by dividing a large panel into the thin-film interconnect structure and one or more other interconnect structures.
Bumps are applied to the surface of the interconnect structure at operation 1220. The bumps may include micro solder bumps and/or copper pillar bumps, and can be provided onto the surface of the interconnect structure that will eventually be bonded to a die (e.g., the bottom surface that is opposite of the ridge carrier.
The thin-film interconnect structure is provided onto a substrate at operation 1230. After fabrication of the thin-film interconnect structure, the thin-film interconnect structure can be transported to a facility for additional processing (e.g., bonding of substrate and dies). The thin-film interconnect structure may be inverted so that the surface having the bumps faces toward the die, and the thin-film interconnect structure and substrate may accordingly be bonded together.
One or more dies are provided onto the thin-film interconnect structure at operation 1240. The dies may be bonded to the surface of the thin-film interconnect structure opposite the other surface to which the substrate is bonded. Prior to bonding the dies, the thin-film interconnect structure-and-substrate assembly can be tested to ensure proper functionality, thereby avoiding the wasteful bonding of dies to a bad component. Once dies are bonded, fabrication of an integrated circuit package may be completed.
Reference may be made to the spatial relationships between various components and to the spatial orientation of various aspects of components as depicted in the attached drawings. However, as will be recognized by those skilled in the art after a complete reading of the present disclosure, the devices, components, members, apparatuses, etc. described herein may be positioned in any desired orientation. Thus, the use of terms such as ‘above’, ‘below’, ‘upper’, ‘lower’, ‘top’, ‘bottom’, or other similar terms to describe a spatial relationship between various components or to describe the spatial orientation of aspects of such components, should be understood to describe a relative relationship between the components or a spatial orientation of aspects of such components, respectively, as the components described herein may be oriented in any desired direction. When used to describe a range of dimensions and/or other characteristics (e.g., time, pressure, temperature, distance, etc.) of an element, operations, conditions, etc. the phrase ‘between X and Y’ represents a range that includes X and Y.
For example, it is to be understood that terms such as “left,” “right,” “top,” “bottom,” “front,” “rear,” “side,” “height,” “length,” “width,” “upper,” “lower,” “interior,” “exterior,” “inner,” “outer” and the like as may be used herein, merely describe points of reference and do not limit the present invention to any particular orientation or configuration. Further, the term “exemplary” is used herein to describe an example or illustration. Any embodiment described herein as exemplary is not to be construed as a preferred or advantageous embodiment, but rather as one example or illustration of a possible embodiment.
Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Example embodiments that may be used to implement the features and functionality of this disclosure will now be described with more particular reference to the accompanying figures.
Similarly, when used herein, the term “comprises” and its derivations (such as “comprising”, etc.) should not be understood in an excluding sense, that is, these terms should not be interpreted as excluding the possibility that what is described and defined may include further elements, steps, etc. Meanwhile, when used herein, the term “approximately” and terms of its family (such as “approximate”, etc.) should be understood as indicating values very near to those which accompany the aforementioned term. That is to say, a deviation within reasonable limits from an exact value should be accepted, because a skilled person in the art will understand that such a deviation from the values indicated is inevitable due to measurement inaccuracies, etc. The same applies to the terms “about” and “around” and “substantially”.
In some aspects, the techniques described herein relate to an apparatus including: an assembly including a substrate, one or more dies, and a thin-film interconnect structure; wherein the thin-film interconnect structure is arranged between the substrate and the one or more dies, and includes one or more polymeric layers and conductive plating.
In some aspects, the techniques described herein relate to an apparatus, wherein the thin-film interconnect structure is provided to the substrate prior to providing the one or more dies to the thin-film interconnect structure.
In some aspects, the techniques described herein relate to an apparatus, wherein the thin-film interconnect structure includes one or more thin-film capacitors.
In some aspects, the techniques described herein relate to an apparatus, wherein the thin-film interconnect structure includes one or more power management dies.
In some aspects, the techniques described herein relate to an apparatus, wherein the assembly is selected from a group consisting of: an application-specific integrated circuit, a silicon photonic packaging, a co-packaged optical module, and a near-package optical module.
In some aspects, the techniques described herein relate to an apparatus, wherein the thin-film interconnect structure is fabricated from a panel that is divided into a plurality of thin-film interconnect structures.
In some aspects, the techniques described herein relate to an apparatus, wherein the substrate includes an organic substrate.
In some aspects, the techniques described herein relate to an apparatus including: a thin-film interconnect structure that includes one or more polymeric layers and conductive plating; a first surface of the thin-film interconnect structure being configured to receive one or more dies; and a second surface of the thin-film interconnect structure being configured to receive a substrate.
In some aspects, the techniques described herein relate to an apparatus, wherein the thin-film interconnect structure includes one or more thin-film capacitors.
In some aspects, the techniques described herein relate to an apparatus, wherein the thin-film interconnect structure includes one or more power management dies.
In some aspects, the techniques described herein relate to an apparatus, wherein the thin-film interconnect structure is included in an assembly including the thin-film interconnect structure, the one or more dies, and the substrate, and wherein the assembly is selected from a group of: an application-specific integrated circuit, a silicon photonic packaging, a co-packaged optical module, and a near-package optical module.
In some aspects, the techniques described herein relate to an apparatus, wherein the thin-film interconnect structure is fabricated from a panel that is divided into a plurality of thin-film interconnect structures.
In some aspects, the techniques described herein relate to an apparatus, wherein the thin-film interconnect structure includes five or more polymeric layers.
In some aspects, the techniques described herein relate to an apparatus, wherein the first surface has a first pad pitch of at least 10 μm or, and wherein the second surface has a second pad pitch of at least 100 μm.
In some aspects, the techniques described herein relate to a method including: providing a thin-film interconnect structure onto a substrate, wherein the thin-film interconnect structure includes one or more polymeric layers and conductive plating; and providing one or more dies onto the thin-film interconnect structure.
In some aspects, the techniques described herein relate to a method, wherein the thin-film interconnect structure is provided to the substrate prior to providing the one or more dies to the thin-film interconnect structure.
In some aspects, the techniques described herein relate to a method, wherein the thin-film interconnect structure includes one or more thin-film capacitors.
In some aspects, the techniques described herein relate to a method, wherein the thin-film interconnect structure includes one or more power management dies.
In some aspects, the techniques described herein relate to a method, further including: obtaining the thin-film interconnect structure by dividing a panel into a plurality of thin-film interconnect structures.
In some aspects, the techniques described herein relate to a method, further including: providing one or more of: micro solder bumps, and copper pillar bumps to a surface of the thin-film interconnect structure.
The above description is intended by way of example only. Although the techniques are illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made within the scope and range of equivalents of the claims.
This application claims priority to U.S. Provisional Application No. 63/240,616, filed Sep. 3, 2021, entitled “Next Generation CPO/NPO/ASIC Packaging,” the entirety of which is incorporated herein by reference.
Number | Date | Country | |
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63240616 | Sep 2021 | US |