Area-Efficient Single-legged SOI MOSFET structure immune to single-event-effects and bipolar latch-up

BACKGROUND OF THE INVENTION

There are two primary approaches to the design of large-periphery Metal-Oxide-Semiconductor (MOS) Transistors; one relies on cascading (or arraying) column of multi-Legs (or multi-Fingers) Gates in parallel to enable delivering the required high output current. The other utilizes one single-legged device having sufficiently large Gate width that enables it to deliver same or similar amount of output current. Major advantage of the former approach is that it ensures a desired “Square-like” footprint for any particular large-periphery Transistor Layout. This provides more ease and flexibility in designing and laying-out such Large-periphery Transistors in any given Integrated-Circuit (IC). It can also reduce the device Gate Resistance, and hence it can boost the device power-gain and Bandwidth. The drawback can come however from an excessive increase of the Capacitive parasitic's with the increase of number of Legs (due to a corresponding increase from Gate-to-Drain and Gate-to-Source overpasses, and the increase of total Gate-to-Bulk parasitic's). This can still impose constraining limit on the device operations at relatively higher frequencies (GHz range) when the number of Legs becomes sufficiently high. Such hit on the Transistor Bandwidth from the multi-Legs Gate designs was described and demonstrated in the work of Kwangseok Han, Jeong-hu Han, Minkyu Je and Hyungcheol Shin, “RF Characteristics of 0.18-μm CMOS Transistors”, Journal of the Korean Physical Society, vol. 40, no. 1, pp. 45-48, January 2002. It is caused simply because the resulting increase of the Capacitive and Gate-to-Bulk parasitic's in the large-periphery multi-Legs MOS Transistor can outweigh its enhancement to Bandwidth that comes from the reduction of its Gate Resistance. A compromise is often sought in laying such very large-periphery devices that are specifically intended to deliver high output currents. It optimizes the width of the Gate-Legs in a Multi-Legs MOS device such that it best balances the effects from its total capacitive and Gate-to-Bulk parasitic's to those of its equivalent total Gate resistance. This technique for Layout optimization was described in the work of: Troels Emil Kolding., “Consistent Layout Techniques for Successful RF CMOS Design”, RF Integrated Systems and Circuits (RISC) Group, Aalborg University, Denmark. Whereas the parasitic's from the large Junction-Capacitances in the Bulk MOS Transistors scale with the increase of their total number of Gate-Legs reducing therefore their bandwidth correspondingly as the periphery of these devices increase (e. g. with more Gate-Legs), the Junction-Capacitances in the multi-Legs Silicon-On-Insulator MOS Transistors are on the other hand effectively suppressed or fully nulled. This causes their bandwidth to reduce with the increase of the number of their multi-Legged Gates due mostly to no other than the corresponding increase from their Gate-to-Drain and Gate-to-Source overpasses and their Gate-to-Bulk parasitic's. This renders consequently the SOI MOS Transistors to favor for higher performance the Layouts that incorporate MOS structures having wider Gate-Legs and reduced number of Legs so to suppress the overpasses and the Gate-to-Bulk parasitic's while pronouncedly enhancing the bandwidth and performance. A whole major issue does arise however with SOI-MOS Transistor designs that incorporate wider Gate-Legs. It is their higher susceptibility to Bipolar latch-up because of their substantially higher impact-ionization currents that are generated around their Drains (the impact-ionization current in each Gate-Leg scales when the width of the Gate-Legs is widened). This is especially true for the case of Fully-Depleted-SOI (FD-SOI) MOS Transistor that inherently possesses an already lowered Body-to-Source barrier due to the full depletion of their Body through which the impact-ionization current diffuses and lowers it further causing this latch-up. This tendency for latch-up in FD-SOI MOS was first reported in the work of C. Fenouillet-Beranger et al., “Parasitic bipolar impact in 32 nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology”, Solid-State Electronics, vol. 74, pp. 32-37, 2012. Such effects from the parasitic Bipolar that is inherent to field-effect MOS Transistors are especially damaging to the integrated Electronics that operate in high radiation environments (high aviation altitudes, outer Space, etc. . . . ). When these Transistors are biased at a high operating bias so they can deliver their best performance, energetic cosmic-rays that can strike even their ultra-thinned Sensitive Silicon Volume (e. g case of ultra-thin FD-SOI MOS Transistors) can induce added ionized charge that will further lower their Body-to-Source lateral barrier and result in many different functional failures or malfunctions (e. g Single-Event-Burnout, Single-Event-Latch, Single-Event-Upset, Single-Event-Transient, Single-Bit-Upset, Multiple-Bit-Upset, Single-Event-Functional-Interrupt); all these modes of failures or malfunctions are commonly referred to as: Single-Event-Effects (SEE's). It was specifically demonstrated by P. E. Dodd et al., “Single-Event-Upset and Snapback in Silicon-on-Insulator Devices”, Sandia National Laboratories, Albuquerque, N. Mex., March 2000, that a combined effect from both impact-ionization current due to high biasing and Single-Event-Effects from Cosmic rays does drastically amplify these failures in an active Silicon film that was 180 nm thick. While other impacts from Cosmic rays that still damage the Electronics (e. g. Total-Ionization-Dose (TID)) take quite long time (months or years) to build their damage on the MOS dielectrics and slowly drift and degrade the performance of the Electronics and devices, the SEE's on the other hand do and can cause an instantaneous and swift failure when they are not very adequately guarded against. Most recent major incident caused by SEE's is the 2008 Cosmic-ray showers on the commercial passenger airline QF72 that prevented it from accurately processing its Angle-of-Attack data. One crew member and eleven passengers suffered serious injuries, while eight crew members and ninety-five passengers suffered minor injuries.

A very adequate Device-level protection against the SEE's can reduce or may even eliminate the need for Redundant-circuitries that are always employed nowadays in all the avionics and the Space electronic systems to tackle the SEE's. Reducing or eliminating these Redundant-circuitries can substantially reduce the die area of integrated-circuits and sensors as well as their power consumptions. It can also make the Electronics smaller and much more compact enabling their more practical deployment everywhere and anywhere in aircrafts, space robots and space vehicles (e.g. in tiny spaces closer to other integrated modules). It can also pave the way for denser system-level integrations that may include much added on-chip functionalities. Even by not reducing any Redundant-circuitries an added Device-level protection against the SEE's will guard further against the failures from these SEE's. This is because many Logic Gates (e. g. those forming decision voters to determine if Logic malfunctions incurred) remain still susceptible to SEE's even when Double-Redundant-Modules (DRM) or Triple-redundant-Modules (TRM) are employed.

The classical fix to this Bipolar latch-up has traditionally been through incorporating a Body-Tied-Source (BTS) implant in the Source-diffusion region and having it interface the device Body under the Gate. This BTS is very highly doped and has same dopant type as the device Body which allows the impact-ionization current to conduct to this BTS away from the lateral Body-to-Source barrier preventing therefore the bipolar latch-up. This approach was well explained in the work of K Hirose et al., “Analysis of Body-Tie Effects on SEU Resistance of Advanced FD-SOI SRAMs Through Mixed-Mode 3D Simulations”, IEEE Trans. Nucl. Sc., vol. 51, no. 6, pp. 3349-3353, December 2004.

Two main issues still exist with this approach:
1—The low electric conductivity of the Body (especially in FD-SOI) that the impact-ionization current sees to BTS can still cause Bipolar latch-up. This is because a high voltage-drop develops in this Body due to the conducting impact-ionization current through this low electric conductance in Body. This had only recently been addressed through U.S. Pat. No. 9,741,857 B2 (Aug. 22, 2017).
2—The “effective” peripheral Width of the Transistor (and therefore its current drive) reduces relative to the total footprint of the device layout. This is because the addition of the BTS region does consume from the Source-diffusion volume that junctions the device Body under the Gate region and reduces it. A set of design-rules that can alleviate for given bias and device periphery this reduction from the “effective” Width of the Transistor were defined through same Patent: U.S. Pat. No. 9,741,857 B2. They were further described by same inventor of this Patent in the publication: Ahmad Houssam Tarakji, “A DC Model of the Planar Dual-Gated FD-SOI MOSFET that Capture the Effects of High Biases and HALO”, Physica Status Solidi (a), January 2018.
However no absolute closed-form (or complete) fix to the above still exists to date.

BRIEF SUMMARY OF THE INVENTION

The invention that is claimed provides a new SOI MOS device architecture that further alleviates the effects from this Bipolar latch-up and with a more or a fully area-efficient design that does not reduce or can reduce least the “effective” peripheral Width of the SOI-MOS field-effect Transistors. Its structure is based on trapping the impact-ionization current in a band-engineered highly doped Pocket that junctions the Source on one side while it interfaces the device Body on its other side along the entire device or (Gate) Width (in similarity to the device design of U.S. Pat. No. 9,741,857 B2). This Pocket has same dopant type as in device Body. It traps and diverts the impact-ionization current directly to the Source (instead of diverting it to BTS as in the MOS device structures of U.S. Pat. No. 9,741,857B2). This diversion occurs through a well-engineered high electrically conductive path between the Body under the Gate region and the Source that uses Silicide formation to directly wire this Pocket to the Source. This design can still effectively divert impact-ionization current away from the lateral Body-to-Source Junction and does not reduce the “effective” Width of the Transistor. It can be valid for the FD-SOI MOS as well as for the Partially-Depleted-SOI MOS (PD-SOI-MOS). Trenched square or rectangular metals (e. g. Tungsten) or any other form of interconnects (e. g. Graphene, etc. . . . ) can also contact the Silicide that wires the highly doped Pocket to Source for a possible even higher electric conductance between the Body under the Gate and the Source.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1a: Cross-section Cartoon of a new structure for SOI MOSFET showing the high doped Pocket and its shunt to the Source-diffusion region with Silicide. Not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions (Since Gate dielectric is excessively ultra-thin any Metal that touches it diffuses and creates effective short(s) to Drain and/or Source). A barrier does exist between the Body under the Gate and the Source. This barrier can be lowered from an impact-ionization current causing a possible Bipolar latch-up unless this impact-ionization current gets diverted away from the barrier. The shortening of the highly doped pocket under the Gate to the Source through Silicide provides this diversion as this figure shows.

FIG. 1
b: Similar device structure as that of FIG. 1a but in which the Silicide does not extend to encompass the entire lateral dimension of the highly doped pocket. (Not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions).

FIG. 2: Cross-section Cartoon of a new structure for SOI MOSFET in which the Silicide covers only a top portion of the Source and does not extend laterally into the highly doped Pocket. (Not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions).

FIG. 3: Cross-section Cartoon of a new structure for SOI MOSFET in which the Silicide covers only a top portion of the Source and extends slightly laterally into the highly doped Pocket. (Not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions).

FIG. 4: Same device structure as that of FIG. 1a but in which a trenched conducting material (e. g. Copper Metals) contact the “back” Silicide in Source region. (Conducting interconnects also contact the opposing side of same Silicide and the Silicide in Drain region to form the Contacts for inline-interconnects are not shown in this figure). (Also not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions).

FIG. 5: Same device structure as that of FIG. 1b but in which raised Silicide is formed on the “back” Silicon. (Not shown in figure are the two Spacers that extend from both edges of the Gate to the Silicide regions).

FIG. 6: A generalized figure summarizing the different steps that are required for the formation of high electrically conducting Silicide.

DETAILED DESCRIPTION OF THE INVENTION

The new device architecture for SOI MOSFET traps the impact-ionization current in a band-engineered highly doped Pocket that extends in the active Silicon underneath the Gate along the entire device Width and routes this impact-ionization current to the Source-diffusion region through a highly electrically conductive path that contains a Silicide formation that solders this Pocket to the Source. This prevents the impact-ionization current from diffusing through the lateral Body-to-Source barrier and lowering it further. The Silicide in Source region can either consume the entire thickness of active Silicon or only the top portion of it. It may also extend laterally into the highly doped Pocket under the Gate. Square or trenched interconnects may also contact the Silicide to further increase the electric conductance between the device Body under the Gate and the Source. The lightly-doped Drain region helps to suppress the injection of Hot-electrons into the Gate. (Lightly doped region(s) may be omitted and replaced with same dopant concentration as in rest of Source and Drain). The FIG. 1a, FIG. 1b, FIG. 2, FIG. 3, FIG. 4 and FIG. 5 illustrate some possible different embodiments for this new device architecture.

Raised Silicide designs relative to either both sides of the active Silicon in Source region or to only a one side of this active Silicon can be used and may even be essential when this active Silicon is ultra-thinned (˜7 nm-35 nm). This prevents the Silicide from diffusing closer underneath the Gate and deteriorating the Gate channel.

Whereas the simpler device structure of FIG. 2 can follow a similar fabrication process to what the today's standard CMOS processes follow provided that some necessary process ramifications are made such to enable the Silicide to form deep into the Silicon and wires to the highly doped Pocket, a more effective wiring of this highly doped pocket to the Source requires more complex processes. In the former process carefully controlled angled Germanium Pre-Amorphousiation Implant (GPI) can be performed after the formation of the Spacer to regulate the depth and the lateral penetration of the Silicide prior to depositing the Metal and the annealing to form Silicide. GPI proved to enable the formation of better Silicide, enables better control for the depth and lateral penetration of Silicide, and prevents or suppresses any metallic pipes from diffusing deeper into the Silicon film closer to the conducting device channel. In the latter process an etch-Stop-Layer (ESL) through the surface of a seed Wafer (that is the Wafer that is to be bounded to a Handle Wafer) is implanted first. This can be followed with the growth of thick epitaxy atop this seed Wafer surface. This epitaxy is the active Silicon film of the MOS device (which can be as ultra-thin as 7-35 nm). Another approach is not to use epitaxy; Carbon is implanted as ESL through the surface of seed Wafer and the portion of Silicon on top of this ESL becomes the active Silicon of the MOS device. Carbon is electrically-inactive in Silicon and when implanted at temperatures close to 500 degC. Crystal damage is lowered or minimized. Other electrically-inactive species (e.g. Nitrogen) can also be implanted instead of Carbon. The surface of the seed Wafer is then thoroughly cleaned—The device Frontend regions are then patterned and implanted and the formation of Silicide that wires the highly doped Pocket to Source can then be accomplished through either one of two separate approaches:

- 1—The Body, Source and Drain diffusion regions are implanted first and the highly doped Pocked is formed (this can either be through patterning it and then implanting it, and/or through using angled implants on deposited Photoresist). The surface is then polished with Chemical-Mechanical Polish (CMP), cleaned and the Silicide that solders this highly doped pocket to the Source is processed.
- 2—The center Body is implanted first. This is followed with growth of high quality Silicon or Silicon-Germanium Epitaxy atop the two lateral side edges of the Silicon. This Epitaxy is then implanted to form the Drain, Source and Pocket regions over which the Silicide is formed next. (This epitaxy may also be grown to form the Source and Pocket regions only atop which the Silicide is formed while the Drain region lays exclusively in the bulk Silicon).

Trenched or rectangular electrically conductive interconnect (e. g. Tungsten, Copper, etc. . . . ) can also contact this Silicide that wires the highly doped Pocket to Source as FIG. 4 shows. Inline dielectric is finally formed or deposited. This Inline dielectric can be thin enough just to enable an effective dielectric-to-dielectric bonding of this seed Wafer to a Handle Wafer. Tough refractory metals that form Silicide stable at high temperatures (˜900-1000 DegC.) can be used in the formation of this back-Silicide. This is because of the much high temperatures that are necessary and required in the continuation of this fabrication process. This Silicide must be stable and capable to withstand the upcoming heat cycles (e.g. the thermal growth of the Gate dielectric, Source/Drain annealing, etc. . . . ). Examples can be: TiSi₂(C₅₄), TaSi₂, MoSi₂, WSi₂, CoSi₂. A technique that boosts the thermal stability of Nickel-Silicide at higher temperatures (˜700-1000 DegC.) may even allow the use of Nickel-Silicide to wire this highly doped pocket to the Source. This requires the deposition of thin Aluminum film (typically ˜3-5 nm thick) onto the Silicon prior to depositing the Nickel and applying the required heat-cycles to form this Nickel-Silicide. This approach was described and demonstrated in the work of Takashi Shiozawa, “Improvement of Thermal Stability of Ni Silicide on Heavily Doped N+-Si”, Iwai Laboratory, Department of Electronics and Applied Physics, pp. 41-59, 2007. Because the deposited Inline dielectric into the surface of the seed Wafer can outgas and creates voids upon being subjected to high temperatures after bonding this seed Wafer to the surface dielectric of a Handle Wafer, this Silicided Seed Wafer undergoes prior to this bonding a high temperature anneal that outgases any by-products or gas molecules that were absorbed during the deposition of this Inline dielectric. This pre-bond anneal is typically anywhere between 800 DegC. and 1200 DegC. but may be lower. CMP is followed next and the Seed and Handle Wafers are then bonded together through their surface dielectrics. A post-bond anneal is then performed to strengthen this bond and the two Wafers become one Wafer. The “back” Silicon of the seed Wafer is then polished. Typically grinding is performed first to thin this “back” Silicon down to 30-50 μm. This grinding can be highly time-efficient in the high-volume manufacturing due to its highest thinning rate. It is a two-step process that includes a coarse grinding (at ˜5 μm/s) and a subsequent fine grinding (at ˜1 μm/s). This second step is necessary to remove most of the damage layer created by the coarse grinding step and to reduce surface roughness. Additional thinning processes are performed next to further thin down this “back” Silicon down to 100-200 nm prior to utilizing MagnetoRheological Finishing (MRF) and/or Plasma Chemical Vaporization Machining (PCVM) for an exact precise thinning of the Silicon film and for minimizing its surface roughness. These additional thinning processes prior to MRF and/or PCVM can include combinations of dry/wet etching and CMP to substantially further reduce the thickness of this “back” Silicon. The purpose of the ESL that was implanted into the Seed Wafer at the very beginning is to impede the etch-rate from these dry/wet etch prior to a precision thinning of the Wafer with MRF and/or PCVM. The ESL layer may also be implanted through the “back” Silicon instead when this “back” Silicon becomes sufficiently thinned, or it may even be omitted all together when a very precise control of the polish steps can be undertaken with a precise use of MRF and/or PCVM). The FIG. 6 shows or illustrates the main processing steps that are involved in this fabrication process. After the active Silicon film is thinned to its targeted/desired thinness through following the steps described above, devices are then fabricated in following the processes that are same or similar to the today's standard processes for fabricating CMOS. The stronger and thermally-stable “back” Silicide can be capable to withstand the elevated 800-1100° C. temperatures that are typically required in processing the Frontend. The Gate dielectric can be thermally grown at temperatures lower than 700-900° C., and the Source-Drain-Annealing (SDAL) temperatures can be slightly lowered to below 900-1000° C. given the much thin volume of the active Silicon compared to that of CMOS devices fabricated on bulk Silicon.

Area-Efficient Single-legged SOI MOSFET structure immune to single-event-effects and bipolar latch-up

Information

Publication Number

Date Filed

Date Published

Inventors

CPC

International Classifications

Abstract

Description

Claims