Claims
- 1. A memory module comprising:
a printed circuit board; a plurality of identical integrated circuits mounted in a first row and a second row onto at least one surface of the printed circuit board; a control logic bus connected to the plurality of identical integrated circuits; and a first register and a second register connected to the control logic bus, the first register accessing a first range and a second range of data bits, the second register accessing a third range and a fourth range of data bits, the first range and the second range of data bits being first and second non-contiguous subsets of a data word, and the third range and the fourth range of data bits being third and fourth non-contiguous subsets of the data word.
- 2. The memory module of claim 1, wherein:
the first range of data bits comprise data bits 0 to 15; the second range of data bits comprise data bits 32 to 47; the third range of data bits comprise data bits 16 to 31; and the fourth range of data bits comprise data bits 48 to 63.
- 3. The memory module of claim 1, wherein the printed circuit board has a line of bilateral symmetry which bisects the printed circuit board into a first lateral half and a second lateral half.
- 4. The memory module of claim 3, wherein the first row is substantially perpendicular to the line of bilateral symmetry.
- 5. The memory module of claim 4, wherein the first row is bilaterally symmetric with respect to the line of bilateral symmetry.
- 6. The memory module of claim 3, wherein the second row is substantially perpendicular to the line of bilateral symmetry.
- 7. The memory module of claim 6, wherein the second row is bilaterally symmetric with respect to the line of bilateral symmetry.
- 8. The memory module of claim 3, wherein the control logic bus comprises a first set of address signal paths which connect the integrated circuits of the first row and the second row on the first lateral half to the first register and the control logic bus comprises a second set of address signal paths which connect the integrated circuits of the first row and the second row on the second lateral half to the second register, the first set of address signal paths and the second set of address signal paths being bilaterally symmetric to one another across the line of bilateral symmetry.
- 9. The memory module of claim 1, wherein the first register addresses the identical integrated circuits located in the first row and in the second row on a first lateral portion of the printed circuit board, and the second register addresses the identical integrated circuits located in the first row and in the second row on a second lateral portion of the printed circuit board.
- 10. The memory module of claim 9, wherein the first lateral portion comprises a first lateral half of the printed circuit board and the second lateral portion comprises a second lateral half of the printed circuit board.
- 11. A method of accessing data bits of a data word, the method comprising:
providing a memory module comprising:
a printed circuit board; a plurality of identical integrated circuits mounted in a first row and a second row onto at least one surface of the printed circuit board; a control logic bus connected to the plurality of identical integrated circuits; and a first register and a second register connected to the control logic bus; accessing a first range of data bits and a second range of data bits using the first register, the first range and the second range of data bits being first and second non-contiguous subsets of the data word; and accessing a third range of data bits and a fourth range of data bits using the second register, the third range and the fourth range of data bits being third and fourth non-contiguous subsets of the data word.
- 12. The method of claim 11, wherein:
the first range of data bits comprise data bits 0 to 15; the second range of data bits comprise data bits 32 to 47; the third range of data bits comprise data bits 16 to 31; and the fourth range of data bits comprise data bits 48 to 63.
- 13. The method of claim 11, wherein the printed circuit board has a line of bilateral symmetry which bisects the printed circuit board into a first lateral half and a second lateral half.
- 14. The method of claim 13, wherein the first row is substantially perpendicular to the line of bilateral symmetry.
- 15. The method of claim 14, wherein the first row is bilaterally symmetric with respect to the line of bilateral symmetry.
- 16. The method of claim 13, wherein the second row is substantially perpendicular to the line of bilateral symmetry.
- 17. The method of claim 16, wherein the second row is bilaterally symmetric with respect to the line of bilateral symmetry.
- 18. The method of claim 13, wherein the control logic bus comprises a first set of address signal paths which connect the integrated circuits of the first row and the second row on the first lateral half to the first register and the control logic bus comprises a second set of address signal paths which connect the integrated circuits of the first row and the second row on the second lateral half to the second register, the first set of address signal paths and the second set of address signal paths being bilaterally symmetric to one another across the line of bilateral symmetry.
- 19. The method of claim 11, wherein the first register addresses the identical integrated circuits located in the first row and in the second row on a first lateral portion of the printed circuit board, and the second register addresses the identical integrated circuits located in the first row and in the second row on a second lateral portion of the printed circuit board.
- 20. The method of claim 19, wherein the first lateral portion comprises a first lateral half of the printed circuit board and the second lateral portion comprises a second lateral half of the printed circuit board.
- 21. A memory module comprising:
a printed circuit board; a plurality of identical integrated circuits mounted in a first row and a second row onto at least one surface of the printed circuit board; means for accessing a first range and a second range of data bits of the plurality of integrated circuits, the first range and the second range of data bits being first and second non-contiguous subsets of a data word; and means for accessing a third range and a fourth range of data bits of the plurality of integrated circuits, the third range and the fourth range of data bits being third and fourth non-contiguous subsets of the data word.
CLAIM OF PRIORITY
[0001] This application is a divisional of U.S. patent application Ser. No. 10/094,512, filed Mar. 7, 2002, the disclosure of which is hereby incorporated in its entirety by reference herein.
[0002] This application is related to U.S. patent application Ser. No. 10/674,240, filed Sep. 9, 2003, U.S. patent application Ser. No. 10/674,082, filed Sep. 29, 2003, and U.S. patent application Ser. No. ______ (Attorney Docket No. NETL.001DV4) filed on even date herewith, each of which is a divisional application of U.S. patent application Ser. No. 10/094,512, filed Mar. 7, 2002.
Divisions (1)
|
Number |
Date |
Country |
Parent |
10094512 |
Mar 2002 |
US |
Child |
10765488 |
Jan 2004 |
US |