Claims
- 1. An on-die circuit comprising:
an input/output loop-back (iolb) circuit to perform input/output (I/O) to an input/output connection; and a multi-step reference voltage generator circuit selectively connectable to apply a reference voltage output thereof to the iolb circuit to perform self-test of at least one input/output (I/O) specification of the die.
- 2. An on-die circuit as claimed in claim 1, where the multi-step reference voltage generator circuit is selectively connectable to apply a multi-step reference voltage output thereof to the iolb circuit to perform an input buffer trip-point self-test of the die.
- 3. An on-die circuit as claimed in claim 2, comprising:
a self-test control unit to control operation of the multi-step reference voltage generator circuit, and to control operation of the input buffer trip point self-test.
- 4. An on-die circuit as claimed in claim 1, comprising:
a normal input buffer provided along the iolb circuit to receive at least a non-self-test input from the input/output connection; a self-test input buffer to receive self-test iolb input from the iolb circuit on a first input thereof; and where the multi-step reference voltage generator circuit is selectably connectable to apply the reference voltage output thereof to a second input of the self-test input buffer.
- 5. An on-die circuit as claimed in claim 4, where the multi-step reference voltage generator circuit is selectively connectable to apply a multi-step reference voltage output thereof to the self-test input buffer to perform an output drive level self-test of the die.
- 6. An on-die circuit as claimed in claim 5, comprising:
a self-test control unit to control operation of the multi-step reference voltage generator circuit, and to control operation of the output drive level self-test.
- 7. An on-die circuit as claimed in claim 4, where the multi-step reference voltage generator circuit is selectively connectable to apply a static reference voltage level output thereof to the self-test input buffer to perform a connection leakage self-test of the die.
- 8. An on-die circuit as claimed in claim 7, comprising:
a self-test control unit to control operation of the multi-step reference voltage generator circuit, and to control operation of the connection leakage self-test.
- 9. An on-die circuit comprising:
an input/output loop-back (iolb) means for performing input/output (I/O) to an input/output connection; and a multi-step reference voltage generator means selectively connectable for applying a reference voltage output thereof to the iolb means to perform self-test of at least one input/output (I/O) specification of the die.
- 10. An on-die circuit as claimed in claim 9, where the multi-step reference voltage generator means is selectively connectable for applying a multi-step reference voltage output thereof to the iolb means for performing an input buffer trip-point self-test of the die.
- 11. An on-die circuit as claimed in claim 10, comprising:
a self-test control means for controlling operation of the multi-step reference voltage generator means, and for controlling operation of the input buffer trip point self-test.
- 12. An on-die circuit as claimed in claim 9, comprising:
a normal input buffer provided along the iolb means to receive at least a non-self-test input from the input/output connection; a self-test input buffer means for receiving self-test iolb input from the iolb means on a first input thereof; and where the multi-step reference voltage generator means is selectably connectable for applying the reference voltage output thereof to a second input of the self-test input buffer.
- 13. An on-die circuit as claimed in claim 12, where the multi-step reference voltage generator means is selectively connectable for applying a multi-step reference voltage output thereof to the self-test input buffer for performing an output drive level self-test of the die.
- 14. An on-die circuit as claimed in claim 13, comprising:
a self-test control means for controlling operation of the multi-step reference voltage generator circuit, and for controlling operation of the output drive level self-test.
- 15. An on-die circuit as claimed in claim 12, where the multi-step reference voltage generator means is selectively connectable for applying a static reference voltage level output thereof to the self-test input buffer for performing a connection leakage self-test of the die.
- 16. An on-die circuit as claimed in claim 15, comprising:
a self-test control means for controlling operation of the multi-step reference voltage generator circuit, and for controlling operation of the connection leakage self-test.
- 17. A system comprising:
at least one item selected from a list of: an electronic package, PCB, socket, bus portion, input device, output device, power supply arrangement and case; and an integrated circuit comprising:
an input/output loop-back (iolb) circuit to perform input/output (I/O) to an input/output connection; and a multi-step reference voltage generator circuit selectively connectable to apply a reference voltage output thereof to the iolb circuit to perform self-test of at least one input/output (I/O) specification of the die.
- 18. A system as claimed in claim 17, where the multi-step reference voltage generator circuit is selectively connectable to apply a multi-step reference voltage output thereof to the iolb circuit to perform an input buffer trip-point self-test of the die.
- 19. A system as claimed in claim 18, comprising:
a self-test control unit to control operation of the multi-step reference voltage generator circuit, and to control operation of the input buffer trip point self-test.
- 20. A system as claimed in claim 17, comprising:
a normal input buffer provided along the iolb circuit to receive at least a non-self-test input from the input/output connection; a self-test input buffer to receive self-test iolb input from the iolb circuit on a first input thereof; and where the multi-step reference voltage generator circuit is selectably connectable to apply the reference voltage output thereof to a second input of the self-test input buffer.
- 21. A system as claimed in claim 20, where the multi-step reference voltage generator circuit is selectively connectable to apply a multi-step reference voltage output thereof to the self-test input buffer to perform an output drive level self-test of the die.
- 22. A system as claimed in claim 21, comprising:
a self-test control unit to control operation of the multi-step reference voltage generator circuit, and to control operation of the output drive level self-test.
- 23. A system as claimed in claim 20, where the multi-step reference voltage generator circuit is selectively connectable to apply a static reference voltage level output thereof to the self-test input buffer to perform a connection leakage self-test of the die.
- 24. A system as claimed in claim 23, comprising:
a self-test control unit to control operation of the multi-step reference voltage generator circuit, and to control operation of the connection leakage self-test.
- 25. A method comprising:
using a die which includes an input/output loop-back (iolb) circuit to perform input/output (I/O) to an input/output connection; and applying a reference voltage output to the iolb circuit using an on-die multi-step reference voltage generator circuit to perform self-test of at least one input/output (I/O) specification of the die.
- 26. A method as claimed in claim 25, comprising applying a multi-step reference voltage output thereof to the iolb circuit using the multi-step reference voltage generator circuit, to perform an input buffer trip-point self-test of the die.
- 27. A method as claimed in claim 26, comprising:
using an on-die self-test control unit to control operation of the multi-step reference voltage generator circuit, and to control operation of the input buffer trip point self-test.
- 28. A method as claimed in claim 25, comprising:
having a normal input buffer provided along the iolb circuit to receive at least a non-self-test input from the input/output connection; having a self-test input buffer receiving self-test iolb input from the iolb circuit on a first input thereof; and applying the reference voltage output of the multi-step reference voltage generator circuit to a second input of the self-test input buffer.
- 29. A method as claimed in claim 28, comprising applying a multi-step reference voltage output of the multi-step reference voltage generator circuit to the self-test input buffer to perform an output drive level self-test of the die.
- 30. A method as claimed in claim 29, comprising:
using an on-die self-test control unit to control operation of the multi-step reference voltage generator circuit, and to control operation of the output drive level self-test.
- 31. A method as claimed in claim 28, comprising applying a static reference voltage level output of the multi-step reference voltage generator circuit to the self-test input buffer to perform a connection leakage self-test of the die.
- 32. A method as claimed in claim 31, comprising:
using an on-die self-test control unit to control operation of the multi-step reference voltage generator circuit, and to control operation of the connection leakage self-test.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] Attention is directed to U.S. patent application ______, (docket numbers 42390.P12894) filed on Mar. 29, 2002, entitled “A METHOD AND APPARATUS FOR PRECISE SIGNAL INTERPOLATION”, having inventors Eddie Y. WANG and Harry MULJONO, which may be related to the present application.
[0002] Further, the present application is a continuation-in-part (CIP) application of prior U.S. patent application ______, (docket numbers P12459; 219.40772X00) filed on Jun. 6, 2002, entitled “ARRANGEMENTS FOR SELF-MEASUREMENT OF I/O TIMING”, having inventors Harry MULJONO and Alper ILKBAHAR.