Claims
- 1. A memory array, comprising:
a plurality of ferroelectric floating-gate memory cells arranged in rows and columns; a plurality of word lines, wherein each word line is coupled to a row of memory cells and wherein each word line is formed at a first level; a plurality of program lines, wherein each program line is coupled to a column of memory cells and wherein each program line is formed at a second level overlying the first level; and a plurality of bit lines, wherein each bit line is coupled to a column of memory cells and wherein each bit line is formed at a third level overlying the second level; wherein each program line is isolated from and orthogonal to each word line; wherein each bit line is isolated from and parallel to each program line; wherein each bit line coupled to a column of memory cells is associated with a program line coupled to that column of memory cells; and wherein each program line is laterally offset from its associated bit line.
- 2. The memory array of claim 1, wherein the memory cells are depletion mode memory cells.
- 3. The memory array of claim 1, wherein the program lines are vertically separated from the word lines by a layer of dielectric material.
- 4. The memory array of claim 3, wherein the dielectric material is selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides.
- 5. The memory array of claim 4, wherein the silicon oxides are doped silicon oxides.
- 6. The memory array of claim 3, wherein the bit lines are vertically separated from the program lines by a further layer of dielectric material.
- 7. A method of writing to a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
applying a programming voltage to a first word line coupled to a control gate of the selected memory cell, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell; applying a fraction of the programming voltage to other word lines coupled to control gates of non-selected memory cells not associated with the first word line; applying a ground potential to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell; and applying the fraction of the programming voltage to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.
- 8. The method of claim 7, wherein the programming voltage is approximately 6V.
- 9. The method of claim 7, wherein the fraction of the programming voltage is approximately ½.
- 10. A method of writing to a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
applying a programming voltage to a first word line coupled to a control gate of the selected memory cell, wherein a gate/source voltage equal to approximately ⅓ the programming voltage is sufficient to cause a reversal of polarity of each memory cell; applying approximately ½ the programming voltage to other word lines coupled to control gates of non-selected memory cells not associated with the first word line; applying a ground potential to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell; and applying approximately ½ the programming voltage to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.
- 11. The method of claim 10, wherein the programming voltage is approximately 6V.
- 12. A method of writing to a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
applying a ground potential to a first word line coupled to a control gate of the selected memory cell; applying a fraction of a programming voltage to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell; applying the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell; and applying the fraction of the programming voltage to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.
- 13. The method of claim 12, wherein the fraction of the programming voltage is approximately ½.
- 14. The method of claim 12, wherein the programming voltage is approximately 6V.
- 15. A method of writing to a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
applying a ground potential to a first word line coupled to a control gate of the selected memory cell; applying approximately ½ a programming voltage to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, wherein a gate/source voltage equal to approximately ⅓ the programming voltage is sufficient to cause a reversal of polarity of each memory cell; applying the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell; and applying approximately ½ the programming voltage to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.
- 16. The method of claim 15, wherein the programming voltage is approximately 6V.
- 17. A method of reading a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
applying a first fraction of a programming voltage to a first word line coupled to a control gate of the selected memory cell, wherein a gate/source voltage equal to the programming voltage is sufficient to cause a reversal of polarity of each memory cell; applying a ground potential to other word lines coupled to control gates of non-selected memory cells not associated with the first word line; applying the first fraction of the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line; and applying a second fraction of the programming voltage to a first bit line coupled to a second source/drain region of the selected memory cell and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.
- 18. The method of claim 17, wherein the first fraction is smaller than the second fraction.
- 19. The method of claim 17, wherein the first fraction is approximately ⅓ and the second fraction is approximately ½.
- 20. The method of claim 17, wherein the programming voltage is approximately 6V.
- 21. A method of reading a selected ferroelectric memory cell in an array of ferroelectric memory cells, the method comprising:
applying approximately ⅓ a programming voltage to a first word line coupled to a control gate of the selected memory cell, wherein a gate/source voltage equal to approximately ⅓ the programming voltage is sufficient to cause a reversal of polarity of each memory cell; applying a ground potential to other word lines coupled to control gates of non-selected memory cells not associated with the first word line; applying approximately ⅓ the programming voltage to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line; and applying approximately ½ the programming voltage to a first bit line coupled to a second source/drain region of the selected memory cell and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.
- 22. A memory device, comprising:
an array of memory cells having a plurality of ferroelectric floating-gate memory cells arranged in rows and columns; a plurality of word lines, wherein each word line is coupled to a row of memory cells and wherein each word line is formed at a first level; a plurality of program lines, wherein each program line is coupled to a column of memory cells and wherein each program line is formed at a second level overlying the first level; and a plurality of bit lines, wherein each bit line is coupled to a column of memory cells and wherein each bit line is formed at a third level overlying the second level; wherein each program line is isolated from and orthogonal to each word line; wherein each bit line is isolated from and parallel to each program line; wherein each bit line coupled to a column of memory cells is associated with a program line coupled to that column of memory cells; and wherein each program line is laterally offset from its associated bit line.
- 23. The memory device of claim 22, wherein the memory cells are depletion mode memory cells.
- 24. The memory device of claim 22, wherein the program lines are vertically separated from the word lines by a layer of dielectric material.
- 25. The memory device of claim 24, wherein the dielectric material is selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides.
- 26. The memory device of claim 25, wherein the silicon oxides are doped silicon oxides.
- 27. The memory device of claim 24, wherein the bit lines are vertically separated from the program lines by a further layer of dielectric material.
- 28. An electronic system, comprising:
a processor; and a memory device coupled to the processor, the memory device comprising:
an array of memory cells having a plurality of ferroelectric floating-gate memory cells arranged in rows and columns; a plurality of word lines, wherein each word line is coupled to a row of memory cells and wherein each word line is formed at a first level; a plurality of program lines, wherein each program line is coupled to a column of memory cells and wherein each program line is formed at a second level overlying the first level; and a plurality of bit lines, wherein each bit line is coupled to a column of memory cells and wherein each bit line is formed at a third level overlying the second level; wherein each program line is isolated from and orthogonal to each word line; wherein each bit line is isolated from and parallel to each program line; wherein each bit line coupled to a column of memory cells is associated with a program line coupled to that column of memory cells; and wherein each program line is laterally offset from its associated bit line.
- 29. The electronic system of claim 28, wherein the memory cells are depletion mode memory cells.
- 30. The electronic system of claim 28, wherein the program lines are vertically separated from the word lines by a layer of dielectric material.
- 31. The electronic system of claim 30, wherein the dielectric material is selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides.
- 32. The electronic system of claim 31, wherein the silicon oxides are doped silicon oxides.
- 33. The electronic system of claim 30, wherein the bit lines are vertically separated from the program lines by a further layer of dielectric material.
RELATED APPLICATIONS
[0001] This application is a divisional of U.S. patent application Ser. No. 09/653,074 filed Aug. 31, 2000 and titled, “Array Architecture for Depletion Mode Ferroelectric Memory Devices,” which is commonly assigned and incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09653074 |
Aug 2000 |
US |
Child |
10205989 |
Jul 2002 |
US |