Claims
- 1. A memory array, comprising:a plurality of ferroelectric floating-gate memory cells arranged in rows and columns; a plurality of word lines, wherein each word line is coupled to a row of memory cells and wherein each word line is formed at a first level; a plurality of program lines, wherein each program line is coupled to a column of memory cells and wherein each program line is formed at a second level overlying the first level; and a plurality of bit lines, wherein each bit line is coupled to a column of memory cells and wherein each bit line is formed at a third level overlying the second level; wherein each program line is isolated from and orthogonal to each word line; wherein each bit line is isolated from and parallel to each program line; wherein each bit line coupled to a column of memory cells is associated with a program line coupled to that column of memory cells; and wherein each program line is laterally offset from its associated bit line.
- 2. The memory array of claim 1, wherein the memory cells are depletion mode memory cells.
- 3. The memory array of claim 1, wherein the program lines are vertically separated from the word lines by a layer of dielectric material.
- 4. The memory array of claim 3, wherein the dielectric material is selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides.
- 5. The memory array of claim 4, wherein the silicon oxides are doped silicon oxides.
- 6. The memory array of claim 3, wherein the bit lines are vertically separated from the program lines by a further layer of dielectric material.
- 7. A memory device, comprising:an array of memory cells having a plurality of ferroelectric floating-gate memory cells arranged in rows and columns; a plurality of word lines, wherein each word line is coupled to a row of memory cells and wherein each word line is formed at a first level; a plurality of program lines, wherein each program line is coupled to a column of memory cells and wherein each program line is formed at a second level overlying the first level; and a plurality of bit lines, wherein each bit line is coupled to a column of memory cells and wherein each bit line is formed at a third level overlying the second level; wherein each program line is isolated from and orthogonal to each word line; wherein each bit line is isolated from and parallel to each program line; wherein each bit line coupled to a column of memory cells is associated with a program line coupled to that column of memory cells; and wherein each program line is laterally offset from its associated bit line.
- 8. The memory device of claim 7, wherein the memory cells are depletion mode memory cells.
- 9. The memory device of claim 7, wherein the program lines are vertically separated from the word lines by a layer of dielectric material.
- 10. The memory device of claim 9, wherein the dielectric material is selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides.
- 11. The memory device of claim 10, wherein the silicon oxides are doped silicon oxides.
- 12. The memory device of claim 9, wherein the bit lines are vertically separated from the program lines by a further layer of dielectric material.
- 13. An electronic system, comprising:a processor; and a memory device coupled to the processor, the memory device comprising: an array of memory cells having a plurality of ferroelectric floating-gate memory cells arranged in rows and columns; a plurality of word lines, wherein each word line is coupled to a row of memory cells and wherein each word line is formed at a first level; a plurality of program lines, wherein each program line is coupled to a column of memory cells and wherein each program line is formed at a second level overlying the first level; and a plurality of bit lines, wherein each bit line is coupled to a column of memory cells and wherein each bit line is formed at a third level overlying the second level; wherein each program line is isolated from and orthogonal to each word line; wherein each bit line is isolated from and parallel to each program line; wherein each bit line coupled to a column of memory cells is associated with a program line coupled to that column of memory cells; and wherein each program line is laterally offset from its associated bit line.
- 14. The electronic system of claim 13, wherein the memory cells are depletion mode memory cells.
- 15. The electronic system of claim 13, wherein the program lines are vertically separated from the word lines by a layer of dielectric material.
- 16. The electronic system of claim 15, wherein the dielectric material is selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides.
- 17. The electronic system of claim 16, wherein the silicon oxides are doped silicon oxides.
- 18. The electronic system of claim 15, wherein the bit lines are vertically separated from the program lines by a further layer of dielectric material.
RELATED APPLICATIONS
This application is a divisional of U.S. patent application Ser. No. 09/653,074 filed Aug. 31, 2000 and titled, “Array Architecture for Depletion Mode Ferroelectric Memory Devices,” which is commonly assigned and incorporated herein by reference now Pat. No. 6,587,365.
US Referenced Citations (33)
Foreign Referenced Citations (2)
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