Patent Application
20230099419
The present disclosure relates to artificial intelligence, and more specifically, to an artificial intelligence device cell. Artificial intelligence devices use phase change materials (PCMs) in cells to store information. For example, the phase of the PCM can be altered or changed to represent changes in stored states or information for the artificial intelligence device. Some PCM materials (e.g., doped germanium-antimony-tellurium (GST)), however, may cause issues for other components of the cell. For example, oxygen from doped GST may damage heaters or the top metal in the cell.
According to an embodiment, an apparatus includes a heater, a phase change material region, and a top metal layer. The phase change material region includes a doped GST layer and a first GST layer. The first GST layer is between the doped GST layer and the heater, and the doped GST layer is doped differently than the first GST layer. The phase change material region is positioned between the heater and the top metal layer. Other embodiments include a method for forming the apparatus.
According to another embodiment, an apparatus includes a heater and a phase change material region. The phase change material region includes a doped GST layer disposed on a first GST layer. The first GST layer is between the doped GST layer and the heater, and the doped GST layer is doped differently than the first GST layer. Other embodiments include a method for forming the apparatus.
This disclosure contemplates an artificial intelligence device cell with a phase change material (PCM) region that includes buffer layers that separate a doped germanium-antimony-tellurium (GST) layer from a heater and top metal in the cell. For example, GST layers may be formed above and below the doped GST layer such that the GST layers are positioned between the doped GST layer and the heater and top metal. The doped GST layer may be doped differently than the other GST layers. For example, the doped GST layer may be doped using silicon dioxide while the other GST layers are undoped or doped using nitrogen or another dopant that does not include oxygen. As a result, the GST layers may prevent the doped GST layer from oxidizing and damaging the heater and the top metal, in certain embodiments.
The processor 102 is any electronic circuitry, including, but not limited to one or a combination of microprocessors, microcontrollers, application specific integrated circuits (ASIC), application specific instruction set processor (ASIP), and/or state machines, that communicatively couples to memory 104 and controls the operation of the computing system. The processor 102 may be 8-bit, 16-bit, 32-bit, 64-bit or of any other suitable architecture. The processor 102 may include an arithmetic logic unit (ALU) for performing arithmetic and logic operations, processor registers that supply operands to the ALU and store the results of ALU operations, and a control unit that fetches instructions from memory and executes them by directing the coordinated operations of the ALU, registers and other components. The processor 102 may include other hardware that operates software to control and process information. The processor 102 executes software stored on the memory 104 to perform any of the functions described herein. The processor 102 controls the operation and administration of the computing system by processing information (e.g., information received from the memory 104). The processor 102 is not limited to a single processing device and may encompass multiple processing devices.
The memory 104 may store, either permanently or temporarily, data, operational software, or other information for the processor 102. The memory 104 may include any one or a combination of volatile or non-volatile local or remote devices suitable for storing information. For example, the memory 104 may include random access memory (RAM), read only memory (ROM), magnetic storage devices, optical storage devices, or any other suitable information storage device or a combination of these devices. The software represents any suitable set of instructions, logic, or code embodied in a computer-readable storage medium. For example, the software may be embodied in the memory 104, a disk, a CD, or a flash drive. In particular embodiments, the software may include an application executable by the processor 102 to perform one or more of the functions described herein.
The system 100 includes a PCM cell 106 (e.g., as part of the memory 104), which may also be referred to as a phase change memory cell. In certain embodiments, the PCM cell 106 is part of the memory 104. The PCM cell 106 includes a PCM that changes phases based on an amount of heat applied to the PCM (e.g., by applying an electric voltage or current to a heating element connected to the PCM). The phase of the PCM cell 106 may be used to represent state or information for an artificial intelligence device. For example, one or more PCM cells 106 may be used to store the different states of a neural network. As another example, one or more PCM cells 106 may be used to store the values in nodes of a graph or tree. The phases of the one or more PCM cells 106 may be adjusted to represent a change in the neural network, graph, or tree. A notable difference between PCM cells 106 and conventional memory is that PCM cells 106 may not be limited to storing binary states (e.g., a 0 or a 1). Rather, the phase of a PCM cell 106 may be used to represent multiple, different states.
The processor 102 and the memory 104 implement a machine learning model 108 that uses the PCM cell 106. For example, the machine learning model 108 may store state information using the PCM cell 106. As the state information changes (e.g., during training of the machine learning model 108), the phase of the PCM cell 106 is adjusted to represent the change in the state information. With enough PCM cells 106, the PCM cells 106 may store the machine learning model 108.
The PCM cell 106 includes a substrate 202 that serves as the foundation of the PCM cell 106. The substrate 202 may include any suitable material (e.g., silicon, metal oxide, or gallium arsenide). Pads 204, 206, and 208 are formed in the substrate 202. The pads 204, 206 and 208 may include any suitable conductive material. The pads 204, 206, and 208 conduct electric currents to or from other components of the PCM cell 106 connected to the pads 204, 206 and 208. A dielectric 209 is disposed on the substrate 202. The dielectric 209 may include any suitable insulative material (e.g., silicon nitride). The dielectric 209 may cover the substrate 202 and the pads 204, 206, and 208.
One or more heaters are formed in the dielectric 209. In the example of
In some embodiments, liners 214 and 216 are formed on the heaters 210 and 212 (e.g., by deposition). The liners 214 and 216 may include a resistive material that improves the resistance drift in the PCM cell 106. The liners 214 and 216 are optional—some embodiments of the PCM cell 106 do not include the liners 214 and 216.
A PCM region 218 is formed on the dielectric 209 and the heaters 210 and 212. The PCM region 218 includes a PCM and protective layers. In the example of
The thickness of the doped GST layer 222 may be greater than the thicknesses of the GST layers 220 and 224. For example, the doped GST layer 222 may be 80 nanometers thick and the GST layers 220 and 224 may each be 1 to 5 nanometers thick. In some embodiments, the doped GST layer 222 is at least ten times as thick as the GST layers 220 and 224. Thus, the GST layers 220 and 224 are thick enough to block oxygen from the doped GST layer 222, but not so thick as to affect the resistance of the doped GST layer 222.
When the pads 206 and 208 apply electrical current to the heaters 210 and 212, the heaters 210 and 212 generate heat. The heat travels to the PCM region 218 and causes the doped GST layer 222 to change phases. By adjusting the electrical current applied to the heaters 210 and 212, the amount of heat applied to the doped GST layer 222 is adjusted. Thus, the phase of the doped GST layer 222 is changed and controlled. The GST layers 220 and 224 protect the heaters 210 and 212, the liners 214 and 216 (if present), and the top metal 226 from oxidation caused by the doped GST layer 222.
A top metal layer 226 is formed on the GST layer 224 (e.g., by deposition). Additionally, a mask 228 is formed on the top metal 226 (e.g., by deposition). Because the doped GST layer 222 is doped differently than the GST layers 220 and 224, the GST layers 220 and 224 protect the heaters 210 and 212 and the top metal 226 from oxidation caused by the doped GST layer 222.
Contacts 230 and 232 are formed in the PCM cell 106 so that electrical connections may be made to the pad 204 and the top metal 226 and mask 228. In the example of
Some embodiments of the PCM cell 106 include a different structure for the PCM region 218.
In block 402, a heater 210 is formed on a pad 206. The pad 206 may be formed in a substrate 202 that serves as the foundation of the PCM cell 106. The heater 210 may include multiple layers of resistive materials. An electric current may be applied from the pad 206 to the heater 210 to cause the heater 210 to generate heat.
In block 404, a GST layer 220 is formed on the heater 210. For example, the GST layer 220 may be deposited on the heater 210. In some embodiments, a liner 214 is formed on the heater 210 before forming the GST layer 220 on the heater 210. In these embodiments, the liner 214 is positioned within the GST layer 220 after the GST layer 220 is formed on the heater 210.
In block 406, a doped GST layer 222 is formed on the GST layer 220. For example, the doped GST layer 222 may be deposited onto the GST layer 220. The doped GST layer 222 includes GST that has been doped with any suitable material (e.g., silicon dioxide or nitrogen). Another GST layer 224 is then formed on the doped GST layer 222 in block 408. In certain embodiments, the GST layer 220, the doped GST layer 222, and the GST layer 224 may all be deposited in one chamber of a semiconductor fabrication process.
In block 410, a top metal 226 is formed on the GST layer 224. In some embodiments, a mask 228 is then formed on the top metal 226. In block 412, a contact 230 is formed above the top metal 226. In some embodiments, the contact 230 is formed on the mask 228 that is formed on the top metal 226. The contact 230 allows an electrical connection to be made to the top metal 226.
In some embodiments, the doped GST layers 222 is significantly thicker than the GST layers 220 and 224. For example, the doped GST layer 222 may be 80 nanometers thick and the GST layers 220 and 224 are 1 to 5 nanometers thick. In some embodiments, the doped GST layer 222 is at least ten times as thick as the GST layers 220 and 224. As a result, the GST layers 220 and 224 protect the heater 210 and the top metal 226 from oxidation caused by the doped GST layer 222. Additionally, the GST layers 220 and 224 do not significantly affect the resistance of the doped GST layer 222.
Heaters 210 and 212 are then formed through the dielectric 209. As seen in
The PCM region 218 is then formed on the dielectric 209. As seen in
As seen in
In summary, an artificial intelligence device cell includes a PCM region 218 that includes buffer layers that separate a doped GST layer 222 from a heater 210 and top metal 226. For example, GST layers 220 and 224 may be formed above and below the doped GST layer 222 such that the GST layers 220 and 224 are positioned between the doped GST layer 222 and the heater 210 and top metal 226. As a result, the GST layers 220 and 224 may prevent the doped GST layer 222 from oxidizing and damaging the heater 210 and the top metal 226, in certain embodiments.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
In the preceding, reference is made to embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to specific described embodiments. Instead, any combination of the features and elements, whether related to different embodiments or not, is contemplated to implement and practice contemplated embodiments. Furthermore, although embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the scope of the present disclosure. Thus, the aspects, features, embodiments and advantages discussed herein are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
