Patent Application
20050268848
1. Field of the Invention
The invention relates to an Atomic Layer Deposition (ALD) apparatus for forming alternating ultra-thin layers on an epitaxial substrate, and to an ALD process in which a gas is adsorbed on an epitaxial silicon substrate to form a first, atomic layer followed by forming a second, ultra-thin epitaxial silicon layer.
2. Description of the Related Art
An ALD apparatus is disclosed in U.S. Pat. Nos. 6,042,652 to Hyun et al. and 6,461,436 to Campbell et al.; and an ALD process is disclosed in Campbell et al. U.S. Pat. No. 6,716,284. These patents use a single reactor (depositing chamber) for ALD.
Production of silicon wafers in a single chamber is described in Yang U.S. Pat. No. 6,599,815.
Apparatus and methods for manufacturing silicon wafers using multiple chambers and a loading chamber are described in Maydan et al. U.S. Pat. No. 4,951,601 and Ihantola U.S. Pat. No. 6,174,366. These patents do not involve ALD techniques, and use different chambers for different sequential steps in silicon wafer production such as chemical vapor deposition and plasma etching. Epitaxial growth occurs in a single one of the multiple chambers in contrast to the apparatus and process of the present invention.
U.S. Pat. No. 5,233,218 discloses a silicon-on-insulator (SOI) type semiconductor wafer which is produced either by an SIMOX (Separation by Implanted Oxygen) process or by laminating two silicon wafers, one having a silicon oxide layer and the other being all silicon.
Structures comprising epitaxially grown alternate layers of SiO2 and Si are disclosed in U.S. Pat. No. 5,216,262 issued to Raphael Tsu.
The following publications describe SOI structures comprising superlattices having alternating epitaxial layers of silicon and oxygen (Si/O):
A superlattice comprising alternating epitaxial layers of silicon and carbon is described in Wang et al. U.S. Provisional Application 60/408,358 and corresponding U.S. application filed thereon on Apr. 14, 2004.
According to the invention there is provided an atomic layer deposition apparatus for depositing a plurality of ultra-thin layers onto an epitaxial substrate, said apparatus comprising: a first chamber having an inlet for a gas to be adsorbed on an epitaxial substrate; a second chamber having an inlet for a gas to be adsorbed on said epitaxial substrate; a transport chamber disposed between said first and second chambers for transporting and annealing said epitaxial substrate; a loading chamber connected to the transport chamber for storing, loading and unloading epitaxial substrates, said loading chamber comprising a vacuum gate for isolating the loading chamber from the external atmosphere; the transport chamber comprising transporting means for transferring epitaxial substrates to and from each of said first, second and loading chambers; the first chamber being connected to the transport chamber by a first conduit and the second chamber being connected to the transport chamber by a second conduit, each conduit allowing passage of substrates and comprising a vacuum gate; an outer chamber enclosing the first, second and transport chambers and at least partially enclosing said loading chamber; means for heating the first, second and transport chambers to temperatures individually selected for each chamber; means for evacuating the first, second, transport, loading and outer chambers to ultra high vacuum pressures individually selected for each chamber.
Also provided according to the invention is an atomic layer deposition process which comprises: moving an epitaxial silicon substrate into a transport chamber located between a first chamber and a second chamber, said chambers being heated and evacuated to ultra high vacuum pressures; transferring the substrate into the first chamber and introducing a gas for adsorption onto the substrate and formation of an adsorbed atomic first layer; transferring the substrate having the first layer back into the transport chamber and then into the second chamber; introducing a silicon-containing gas into the second chamber for adsorption onto the first layer and formation of an ultra-thin epitaxial silicon second layer; maintaining different temperatures in the first and second chambers, said different temperatures being selected to form the first and second layers and maintain them without structural degradation.
According to the invention there is provided an atomic layer deposition apparatus for depositing a plurality of ultra-thin layers onto an epitaxial substrate, said apparatus comprising: a load stack which contains wafers that can be fed into a cyclical transport path, which commences with a series of several heating plates that will increase the wafer temperature from 450° C. to 650° C. or 850° C.; a silicon deposition stack where the top wafer in the stack receives silicon ions or silane vapor at the elevated temperature; from the bottom of the stack, a series of temperature controlled plates that will reduce the temperature of the wafer to 150° C.; an optional wafer removal/unload stack; or an oxygen deposition half stack loading upwards; a heating plate to raise the temperature of the wafer to 350° C. feeding into an optional a carbon deposition half stack loading upwards: a transport from the top of the optional carbon deposition half stack to the series of heating plates that begin the cycle to enter the silicon deposition chamber. The silicon deposition using either silicon ions or silane gas is achieved by ALD at the top of the stack. The oxygen deposition and optional carbon deposition are achieved by CVD throughout the half stack units. One cycle round of this unit provides an atomic layer of silicon, an atomic layer of oxygen and finally, the optional carbon to produce a multilayered Si/O or Si/C wafer. The entire cyclical system is contained in a chamber system providing a vacuum of 1×10−6 Torr or better.
SOI, or silicon-on-insulator, was originally developed for radiation hardening. In a depleted semiconductor region, the depth of the depletion is proportional to the level of random ionizing radiation signals, and an insulation layer placed beneath the epi-surface layer would terminate the depletion thickness at the insulation and reduce the signals created by the random electron-hole pairs generated in the depletion thickness. Over the decades, as the device dimensions reduced from 10s of μm with ever increasing speed, the cross-talk between devices became a serious limiting factor for high speed performance. The use of SOI wafers helps isolate the devices from each other and from the bulk substrate and eliminates the need for shallow trench isolation. Among other benefits, it allows more room for smaller, faster devices with reduced processing steps.
SOI wafers were originally produced under the SIMOX process, by implantation of oxygen ions to a wafer surface to form a buried oxygen (BOX) layer. The implantation of oxygen would crack the top epi-layer of the wafer beyond repair (anneal), and reduce the mobility of the material by more than 50%. In addition, the non-uniformity of the insulating thickness and of the top epi-layer, make the SOI wafer produced under the SIMOX process unattractive. In 2001, the process was modified to perform the ion implantation of oxygen at an elevated temperature in order to provide the silicon atoms with sufficient surface mobility to repair the scattering damages from oxygen ions as soon as they are created. Also the quality of the ion beam was improved and now the SOI wafers from the SIMOX process have become a viable product.
The most well known SOI product currently is bonded wafers. This approach uses two silicon wafers A and B. First a thin SiO2 layer is placed on A, and the A surface with SiO2 is bonded to wafer B. Protons are implanted into the back side of the B and the bonded wafer is annealed in order to peal off most of the B part. The part of the B wafer being pealed off is used for the next wafer A to support a new SiO2 surface layer, while the B part remaining on the first A is polished and coated with an epi-surface (epi-wafer) treatment. Chemical and mechanical polishing is used to shave the top layer of the bonded wafers from a μm to a level of 50 nm or so with reasonable yield. But the bonding, the cut and the shaving are costly procedures.
With a bandgap of 9.2 eV, SiO2 is one of the best insulating materials. Unfortunately, it has a lattice mismatch of 38% with silicon, and cannot be made epitaxially when added to silicon. The growth of SiO2 on silicon is necessarily amorphous, and contains a very high level of dangling bonds because of the lattice mismatch. These dangling bonds must be passivated with hydrogen in order to be useful as MOS for device fabrications. MOS has become the basic structure for silicon devices. Using a Si/O superlattice, even having oxygen participating in less than 1/10 of the layers, the bandgap of Si/O is already at 2.3 eV. Using a bandgap of 2.3 eV for Si/O its breakdown voltage may be estimated to be approximately 3.5 MV/cm as scaled from that of SiO2 at 9.2 eV and 10 MV/cm, including a 38% difference in lattice dimensions. This Si/O superlattice has a lattice mismatch at under 1% and can be made with very low interface defect density. The present invention is directed to make an epi-SOI wafer with an ultra-thin epi-insulator as well as ultra-thin epi-silicon layers because of great need for such an epi-SOI. While the current method of producing SOI must struggle to reach ultra-thin layers, the epi-SOI process starts with the deposition of a single atomic layer uniformly and at low cost.
The epi-SOI made with the apparatus or by the process of the present invention can meet the goals of providing ultra uniform and ultra thin parameters for both the insulating layer and the top epi-layer. Superlattice technology can provide the thickness to a controlling accuracy of a single atomic layer, and can do the fabrication at a greatly reduced cost as compared to the current methods mentioned above.
We have used multi-chamber MBE (molecular beam epitaxy) equipment in research to make an Si/O superlattice, but MBE has a low throughput and cannot satisfy usual silicon processing needs. Therefore, we have found it necessary to use an HV-CVD (high vacuum-chemical vapor deposition), or an atomic layer deposition (ALD) where the silicon deposition can be controlled at atomic level. The ALD apparatus according to the invention includes a separate chamber for, e.g., oxygen exposure without contaminating, e.g., silicon deposition done in a second chamber. These two chambers are separated by a gate-lock which may be injected with inert gas.
For binary superlattice fabrication, the invention provides a first chamber for one gas and a second chamber for another gas, in a way without mixing the gases. Between the chambers is a transport chamber which receives substrates, e.g., silicon wafers, from the two gas adsorption chambers, rotates them and sends them back to one or the other of the adsorption chambers. Wafers in the three chambers are kept at different temperatures, with the higher temperature for thermal cracking of e.g. silane which can be injected by an insulated nozzle, and the lower temperatures used for exposure to a gas such as oxygen. The transport chamber has three rectangular gates one for each gas adsorption chamber and one for wafer loading. As shown in
For a silicon-based superlattice using an extremely thin layer of foreign atoms to be sandwiched between epi-layers of silicon, the ultra-thin layer of foreign atoms can be made self-limiting when the catalytic function of the silicon surface structure is employed, and the foreign atoms can be large foreign molecules. Allowing the catalytic function to operate at 700° C. or more, the foreign molecules would undergo thermal cracking on the silicon surface so that the deposition process can occur under the usual CVD instead of exclusively under the MBE. While silicon does not have a direct bandgap for strong optical emissions, the silicon-based superlattices do provide very strong and steady opto-luminescence with wavelength mostly in the visible range. These emissions also confirm the atomic arrangement of the superlattice surface.
In the process of the invention, the ultra high vacuum pressures typically are such that:
Thus mixing of the different gases is avoided, and following adsorption of introduced gases, residual gases in the first and second chambers may be removed by evacuation.
Known apparatus using a highly evacuated chamber or multiple chambers must be constructed to withstand a high pressure difference with respect to the atmosphere, and to have substantial insulation.
Atmospheric pressure is 760 torr, (14.51 lbs/inc2). At a chamber vacuum of one torr or less, the known apparatus chamber wall must sustain 760−1=759 torr (14.51 lbs/inch2). For a large vacuum chamber, the pressure burden can be tons on the wall, and the wall must be spherical. Otherwise, a flat wall even with an inch thick steel would still be pressed to become warped. A large, round chamber wall is difficult to connect with flat openings such as the glass windows, vacuum sealed gates, transport ports, etc. so the vacuum chamber is usually constructed as small as possible. Also in known apparatus, inside the chamber samples may be maintained at 700° C. or higher, while the chamber wall is exposed to room temperature. The wall can be only a few cm away from the hot sample. The sample must therefore, be heated aggressively and the chamber wall must be cooled aggressively in order to maintain such a large temperature difference. In addition, the sample temperature must be kept uniformly throughout its surface. Combining all the requirements, they become a costly and almost impossible task.
However, in the apparatus of the present invention the outer chamber may comprise a wall, usually spherical, constructed of steel sufficiently thick to withstand a pressure difference between a pressure inside said chamber of between about 10−8 torr and about 10−9 torr, and atmospheric pressure outside said chamber. The outer chamber may be insulated in some cases. The first, second and transport chambers then may be made of thin rectangular stainless steel “shoeboxes”. The walls of these boxes do not need to endure 14.51 lbs/inch2, but only the pressure difference (or gradient) between 10−3 torr and 10−9 torr. The boxes are kept e.g. at 500-700° C. so that the sample can readily be maintained at a uniform temperature, the same as the box wall. Outside the shoeboxes the outer chamber pressure is very low. At low pressure, gases would not conduct much heat, so that the outer housing can be kept at room temperature without much need for cooling or insulation.
More particularly, the first, second and transport chambers may be constructed of thin steel having a thickness sufficient to withstand a pressure difference between a pressure inside each said chamber of between about 10−3 torr to about 10−6 torr and a pressure outside each chamber of between about 10−8 torr and about 10−9 torr.
Temperatures maintained in the first, second and transport boxes will vary depending on the gases and substrates being processed. Typically:
In accordance with the invention, the epitaxial substrate may be epitaxial silicon, typically a silicon wafer.
The gas supplied to the first chamber may comprise an element selected from the group consisting of oxygen, carbon, nitrogen, phosphorus, sulfur, hydrogen, antimony, arsenic, aluminum, erbium, germanium, hafnium, rubidium and zirconium, and combinations thereof. Usually, the gas is oxygen or comprises carbon. A silicon-comprising compound may be supplied in gaseous form to said second chamber.
In the apparatus, the gas inlet to the second chamber to supply a gaseous silicon-comprising compound may also comprise means for delivering the gaseous silicon compound through said nozzle in a series of pulses of said compound in selected amounts. The means may be a programmed electrical switch. ALD is really a HV-CVD where the silane gas pressure is reduced to 10−3 torr or so. In fact, the silane gas such as SiH4 can be delivered to the heated wafer surface by a gaseous pulse from a nozzle so that the wafer surface will receive uniformly one or two atomic layers for each pulse. The wafer surface preferably is kept at a very uniform temperature in order to achieve a uniform thermal cracking of the silane. The chamber walls are also at the wafer temperature, therefore the chamber walls will also be exposed and coated with silicon. The walls can be scrubbed periodically if necessary.
After adsorption of a first and second layer on the substrate, formation of layers in the first and second chamber may be repeated to form a plurality of periods each comprising alternating first and second layers. In such repeated alternating layers, the gas adsorbed in the first layer forming part of the first period, may form layers in succeeding periods, or a different gas may be used in the first chamber. For example, in production of a superlattice a phosphorous layer may be formed e.g. to stop oxygen atoms in Si/O layers from diffusing out.
By formation of a plurality of periods a superlattice can be formed on the substrate. The superlattice may comprise a plurality of epitaxially grown silicon layers sandwiched between adsorbed monolayers of oxygen. The superlattice may comprise between about 9 periods and about 100 periods. Instead of a Si/O superlattice, a Si/C superlattice may be formed, wherein the superlattice comprises a plurality of epitaxially grown silicon layers sandwiched between adsorbed monolayers of carbon. The Si/C superlattice may comprise between about 9 periods and about 100 periods.
The Si/O superlattice can be fabricated with a few Si layers per each atomic oxygen layer as an insulator or a few tens of silicon layers per atomic oxygen layer as a high-resistive silicon material.
The apparatus as shown in
Substrates such as silicon wafers can be held by thin metal plates made of stainless steel or molybdenum, with the back of the plate having a handle that can be reached by mechanical arms to position the plate in the chambers and to pass it through the gate-lock between the chambers. Heating of the wafer can be resistive of the plate via RF induced eddy currents in the metal. Gaseous silane may be delivered through a thermally insulated nozzle with electrical switch so that the gas source will be delivered in the form of a precise pulse with minimal residual gas flow.
The chambers as well as the outer housing are kept at UHV under turbo molecular pumps.
Reference is next made to
With a much larger bandgap than silicon, Si/O and SiC can be used to construct devices serving high power and high temperature operations that silicon devices cannot. Conventional silicon oxide on silicon is amorphous and the SiC material is a very difficult crystal to construct. SiC does not have a liquid phase except at 2,800° C. and under 38 atmospheres of pressure so that it cannot form a single crystal ingot like silicon and be sliced into wafers. SiC powder is a low-cost grinding material, and its sublimation vapor at 1,800° C. can be used to grow SiC wafer from a template. Such SiC wafers, however, suffer from defects such as micropipes, high dislocation density, polytype, etc., caused mainly by the high temperature growth environment. More recent CVD using binary gas source(s) can reduce the thermal budget to 1,500° C. and below and thereby greatly reducing the SiC defect densities.
Using the silicon-based superlattice, the Si/O and Si/C superlattices make use of the silicon processing environment. They will grow from a silicon substrate to form the Si/O superlattice or will use the Si/O superlattice surface as an intermediate link to attach carbon-containing molecules such as CH4 or C2H4. Note that, as oxygen absorbed on a silicon surface will be self-limiting at low temperature, the carbon-containing molecules attaching only to the oxygen treated surface will also be self-limiting. To incorporate molecules with a self-limiting process is an important aspect of this ALD disclosure, as it makes the controls of incorporating the gas source(s) to the crystal growth relatively simple.
Si/C Deposition Using Intermediate Si/O Superlattice
The Si/C superlattice is constructed on a silicon epi-wafer surface with monolayer of carbon coated on the lattice sites of oxygen in the Si/O structure, which in turn was constructed on the epi-silicon surface using its dimer formation as a catalyst. All molecular binding energies considered here are taken at the room temperature, but can be scaled to review the binding energies at slightly elevated temperatures in order to indicate various reaction possibilities. A bond with one eV is approximately 100 kJ/mole (96.375 kJ/m see for example, Handbook of Physics and Chemistry, CRC Press).
At 650° C., surface silicon atoms would have sufficient mobility to move around and fall into the epitaxial state and location. The surface silicon would again form the dimer structure while cleaving off the H2 gas, completing the superlattice formation for one period and be ready for the construction of the next period.
This application claims the benefit of U.S. Provisional Application No. 60/566,108 filed Apr. 28, 2004 and incorporates the same by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60566108 | Apr 2004 | US |
