Claims
- 1. A method for testing a control logic cache design, comprising the steps of:determining a list of all possible input transactions having an effect on the state of the cache; determining an initial cache state; determining an initial sequence of input transactions to reach the initial cache state; initializing a list of legal cache states with the initial cache state; generating a list of allowed states by associating the list of all possible input transactions with each legal cache state, starting with the initial cache state; generating a sequence of input transactions for each allowed state capable of changing the state of the cache from the initial cache state to the allowed state; generating a series of test sequences from the list of allowed states and their corresponding sequence of input transactions; applying the series of test sequences to the control logic cache design and to a reference memory; comparing response of the control logic cache design and the reference memory to the series of test sequences; and determining a cache control logic design error if the response of the control logic cache design fails to match the response of the reference memory.
- 2. The method of claim 1, wherein:said step of generating a list of allowed states includes initializing the sequence of input transactions for the initial state as the initial sequence of input transactions; initializing a list of search cache states with the initial cache state; and applying each input transaction sequentially to a current search cache state until all input transactions of the list of input transactions have been applied to the current search cache state and if application of an input transaction to the current search cache results in a new cache state not in the list of legal cache states, then listing the resulting state in the list of legal cache states and the list of search cache states, and generating a sequence of input transactions for the new cache state from the sequence of input transactions for the current cache state and the current input transaction, until each input transaction has been applied to the current search cache state, thereupon setting a current search cache state as a next cache state in the search cache state list, and until all cache states in the search cache state list have had all input transactions applied thereto.
- 3. A method for determining all legal states of a control logic cache design, comprising the steps of:determining a list of all possible input transactions having an effect on state of the cache; determining an initial cache state; determining an initial sequence of input transactions to reach the initial cache state; generating a list of allowed states by associating the list of all possible input transactions with each legal cache state, starting with the initial cache state, said step of generating a list of allowed states including initializing a list of legal cache states with the initial cache state; initializing the sequence of input transactions for the initial state as the initial sequence of input transactions; initializing a list of search cache states with the initial cache state; applying each input transaction sequentially to a current search cache state until all input transactions of the list of input transactions have been applied to the current search cache state and if application of an input transaction to the current search cache results in a new cache state not in the list of legal cache states, then listing the resulting state in the list of legal cache states and the list of search cache states, and generating a sequence of input transactions for the new cache state from the sequence of input transactions for the current cache state and the current input transaction, until each input transaction has been applied to the current search cache state, thereupon setting a current search cache state as a next cache state in the search cache state list, and until all cache states in the search cache state list have had all input transactions applied thereto; and generating a sequence of input transactions for each allowed state capable of changing the state of the cache from the initial cache state to said allowed state.
Parent Case Info
This application claims priority under 35 U.S.C. 119(e)(1) from U.S. Provisional Patent Application No. 60/144,568 filed Jul. 15, 1999.
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