Patent Application
20240421036
Memory devices are used in a wide variety of applications. Memory devices are made up of a plurality of memory cells that are typically arranged in an array of a plurality of rows and a plurality of columns. One type of memory cell includes a dynamic random access memory (DRAM) cell. In some applications, a DRAM cell-based memory device may be selected as opposed to other types of memory cell-based memory devices due to DRAM cell's lower cost, smaller area, and ability to hold a greater amount of data relative to, for example, a static random access memory (SRAM) cell or another type of memory cell.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A dynamic random access memory (DRAM) memory cell is a type of volatile memory cell that typically includes a transistor connected in series with a capacitor. This may be referred to as a one transistor-one capacitor (1T-1C) DRAM cell. The capacitor in a 1T-1C DRAM cell functions as a storage device by selectively storing electric charge. The capacitor may be charged through the transistor, and the amount of charge that is stored in the capacitor may be sensed by discharging the charge that is stored by the capacitor. The logical value (e.g., a 1-value or a 0-value) stored by the 1T-1C DRAM cell may correspond to the amount of charge that is stored by the capacitor.
A DRAM memory cell array may be implemented in a back end region (sometimes referred to as a back end of line (BEOL) region) of a semiconductor device. Peripheral circuitry may be included under the DRAM memory cell array, and may include circuits such as sense amplifier circuits, row decoder circuits, column decoder circuits, and/or address decoder circuits, among other examples. Including the peripheral circuitry under the DRAM memory cell array (a configuration that may be referred to as a circuit under array (CuA)) may enable the horizontal size of the semiconductor device to be reduced relative to if the peripheral circuitry were included adjacent to and/or around the DRAM memory cell array.
While a DRAM memory cell array may provide volatile memory for caching and other functions in a back end region of a semiconductor device, the data stored in the DRAM memory cell array is lost when power is removed from the semiconductor device due to the volatile nature of DRAM.
In some implementations described herein, a semiconductor device may include a non-volatile memory structure that may be formed in a BEOL region of a semiconductor device. The non-volatile memory structure may include a dielectric-based one-time programmable (OTP) anti-fuse memory structure or a dielectric-based resistive random access memory (ReRAM), among other examples. The non-volatile memory structure may be selectively programmed based on modifying an electrical resistance of the non-volatile memory structure, and may retain data stored in the non-volatile memory structure even when electrical power is removed from the semiconductor device.
The non-volatile memory structure may include a gate structure, a channel region, and a plurality of source/drain regions. A first source/drain region may be electrically coupled with the channel region and a source/drain interconnect structure that electrically connects the first source/drain region with a bit line conductive structure. A second source/drain region may be electrically coupled with the channel region. The second source/drain region may be formed such that the second source/drain region is not physically coupled or electrically coupled with a select line conductive structure. Instead, a portion of a dielectric layer in the BEOL region of the semiconductor device is included between the second source/drain region and the select line conductive structure such that the second source/drain region and the select line conductive structure are physically and electrically isolated.
The portion of the dielectric layer between the second source/drain region and the select line conductive structure functions as a programmable resistance-based memory cell region of the non-volatile memory structure. A voltage may be pulsed on the gate structure, which causes current pulses to flow through the channel region from the first source/drain region to the second source/drain region. The current pulses cause an electric field to repeatedly modify the electrical resistance in the portion of the dielectric layer between the second source/drain region and the select line conductive structure until the portion of the dielectric layer breaks down (either reversibly in the case of a programmable ReRAM implementation or permanently in the case of an OTP anti-fuse implementation) and becomes a conductive path from the second source/drain region to the select line conductive structure. In this way, the electrical resistance of the non-volatile memory structure is modified, thereby enabling selective storage of a logical value (e.g., a “0” value or a “1” value) in the non-volatile memory structure.
As described herein, the non-volatile memory structure may be included in the BEOL region of the semiconductor device along with a volatile memory structure (e.g., a DRAM memory structure), such that caching and long-term storage may be performed in the BEOL region of the semiconductor device. The non-volatile memory structure and the volatile memory structure may be formed by similar processing techniques and in the same operations without additional masking steps, which may reduce the complexity of forming the non-volatile memory structure and may result in minimal impact to back end processing cost and time for the semiconductor device.
The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some implementations, the deposition tool 102 includes a spin coating tool that is capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool 102 includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some implementations, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the deposition tool 102 includes an epitaxial tool that is configured to form layers and/or regions of a device by epitaxial growth. In some implementations, the example environment 100 includes a plurality of types of deposition tools 102.
The exposure tool 104 is a semiconductor processing tool that is capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source, an extreme UV light (EUV) source, and/or the like), an x-ray source, an electron beam (e-beam) source, and/or the like. The exposure tool 104 may expose a photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include a pattern for forming one or more structures of a semiconductor device, may include a pattern for etching various portions of a semiconductor device, and/or the like. In some implementations, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.
The developer tool 106 is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some implementations, the developer tool 106 develops a pattern by removing unexposed portions of a photoresist layer. In some implementations, the developer tool 106 develops a pattern by removing exposed portions of a photoresist layer. In some implementations, the developer tool 106 develops a pattern by dissolving exposed or unexposed portions of a photoresist layer through the use of a chemical developer.
The etch tool 108 is a semiconductor processing tool that is capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etch tool 108 may include a wet etch tool, a dry etch tool, and/or the like. In some implementations, the etch tool 108 includes a chamber that is filled with an etchant, and the substrate is placed in the chamber for a particular time period to remove particular amounts of one or more portions of the substrate. In some implementations, the etch tool 108 may etch one or more portions of the substrate using a plasma etch or a plasma-assisted etch, which may involve using an ionized gas to isotropically or directionally etch the one or more portions.
The planarization tool 110 is a semiconductor processing tool that is capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, a planarization tool 110 may include a chemical mechanical planarization (CMP) tool and/or another type of planarization tool that polishes or planarizes a layer or surface of deposited or plated material. The planarization tool 110 may polish or planarize a surface of a semiconductor device with a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The planarization tool 110 may utilize an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring (e.g., typically of a greater diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head may rotate with different axes of rotation to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planar.
The plating tool 112 is a semiconductor processing tool that is capable of plating a substrate (e.g., a wafer, a semiconductor device, and/or the like) or a portion thereof with one or more metals. For example, the plating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and/or the like) electroplating device, and/or an electroplating device for one or more other types of conductive materials, metals, and/or similar types of materials.
Wafer/die transport tool 114 includes a mobile robot, a robot arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated materially handling system (AMHS), and/or another type of device that is configured to transport substrates and/or semiconductor devices between semiconductor processing tools 102-112, that is configured to transport substrates and/or semiconductor devices between processing chambers of the same semiconductor processing tool, and/or that is configured to transport substrates and/or semiconductor devices to and from other locations such as a wafer rack, a storage room, and/or the like. In some implementations, wafer/die transport tool 114 may be a programmed device that is configured to travel a particular path and/or may operate semi-autonomously or autonomously. In some implementations, the example environment 100 includes a plurality of wafer/die transport tools 114.
For example, the wafer/die transport tool 114 may be included in a cluster tool or another type of tool that includes a plurality of processing chambers, and may be configured to transport substrates and/or semiconductor devices between the plurality of processing chambers, to transport substrates and/or semiconductor devices between a processing chamber and a buffer area, to transport substrates and/or semiconductor devices between a processing chamber and an interface tool such as an equipment front end module (EFEM), and/or to transport substrates and/or semiconductor devices between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some implementations, a wafer/die transport tool 114 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-clean processing chamber (e.g., for cleaning or removing oxides, oxidation, and/or other types of contamination or byproducts from a substrate and/or semiconductor device) and a plurality of types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations). In these implementations, the wafer/die transport tool 114 is configured to transport substrates and/or semiconductor devices between the processing chambers of the deposition tool 102 without breaking or removing a vacuum (or an at least partial vacuum) between the processing chambers and/or between processing operations in the deposition tool 102, as described herein.
In some implementations, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may form a word line conductive structure in a semiconductor device, may form a plurality of BEOL dielectric layers over the word line conductive structure, may form, over the word line conductive structure, a recess through the plurality of BEOL dielectric layers to expose the word line conductive structure through the recess, may form a gate structure, of a non-volatile memory structure of the semiconductor device, in the recess such that the gate structure is coupled with the word line conductive structure, may form a first source/drain region and a second source/drain region of the non-volatile memory structure over the gate structure, may form a first interconnect structure on the first source/drain region, may form a bit line conductive structure over the first interconnect structure such that the bit line conductive structure is physically coupled with the first interconnect structure, where the bit line conductive structure is formed in a BEOL dielectric layer of the plurality of BEOL dielectric layers, may form a select line conductive structure in the BEOL dielectric layer, and/or may form a second interconnect structure in the BEOL dielectric layer and on the second source/drain region, where the second interconnect structure is formed such that the second interconnect structure and the select line conductive structure are spaced apart by the BEOL dielectric layer.
As another example, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may form a gate dielectric layer of the non-volatile memory structure over the gate structure, may form a channel layer of the non-volatile memory structure over the gate dielectric layer, and may form the first source/drain region and the second source/drain region over the channel layer. As another example, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may form a gate structure, of a volatile memory structure of the semiconductor device, in the plurality of BEOL dielectric layers, where the gate structure of the non-volatile memory structure and the gate structure of the volatile memory structure are formed in a same set of semiconductor processing operations.
As another example, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may form a first source/drain region and a second source/drain region of a volatile memory structure of the semiconductor device, where the first source/drain region and the second source/drain region of the non-volatile memory structure and the first source/drain region and the second source/drain region of the volatile memory structure are formed in a same set of first semiconductor processing operations. As another example, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may form a first interconnect structure for the non-volatile memory structure on the first source/drain region of the non-volatile memory structure, where the first interconnect structure of the non-volatile memory structure and the first interconnect structure of the volatile memory structure are formed in a same set of second semiconductor processing operations. As another example, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may form a second interconnect structure for the non-volatile memory structure on the second source/drain region of the non-volatile memory structure, wherein the second interconnect structure of the non-volatile memory structure and the second interconnect structure of the volatile memory structure are formed in a same set of third semiconductor processing operations.
In some implementations, one or more of the semiconductor processing tools 102-112 and/or the wafer/die transport tool 114 may perform one or more other semiconductor processing operations described herein, such as in connection with
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A volatile memory structure 206 in the volatile memory array 202 may include a gate structure 210, a channel layer 212 above the gate structure 210, and a plurality of source/drain regions 214 and 216 above the channel layer 212. The gate structure 210, the channel layer 212, and the source/drain regions 214 and 216 may correspond to a transistor of the volatile memory structure 206. A source/drain region, as used herein, may refer to a source region, a drain region, or both a source region and a drain region, depending on the context. The volatile memory structure 206 may further include an interconnect structure 218 above the source/drain region 214, an interconnect structure 220 above the source/drain region 216, a bit line conductive structure 222 above the interconnect structure 218, and a capacitor structure 224 above the interconnect structure 220. The interconnect structure 218 may electrically couple the transistor of the volatile memory structure 206 with the bit line conductive structure 222, and the interconnect structure 220 may electrically couple the transistor of the volatile memory structure 206 with the capacitor structure 224. The capacitor structure 224 may be configured to selectively store an electrical charge for the volatile memory structure 206, enabling one or more logical values to be stored by the volatile memory structure 206 based on an amount of electrical charge stored in the capacitor structure 224. The capacitor structure 224 may be referred to as a programmable charge-based memory cell of the volatile memory structure 206.
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The non-volatile memory structure 208 may further include an interconnect structure 234 above the source/drain region 230, an interconnect structure 236 above the source/drain region 232, a bit line conductive structure 238 above the interconnect structure 234, and a select line conductive structure 240 adjacent to the interconnect structure 236. The interconnect structure 234 may electrically couple the transistor of the non-volatile memory structure 208 with the bit line conductive structure 238.
The interconnect structure 236 may be spaced apart from a select line conductive structure 240 in the non-volatile memory array 204 such that a gap is included between the interconnect structure 236 and the select line conductive structure 240. The gap may include a dielectric region in the BEOL region of the semiconductor device 200, and may be configured as a programmable resistance-based memory cell region 242 of the non-volatile memory structure 208.
The electrical resistance of the programmable resistance-based memory cell region 242 may correspond to a first logic value (e.g., a “0” value or a “1” value). One or more electrical pulses (e.g., current pulses, voltage pulses) may be provided to the programmable resistance-based memory cell region 242, resulting in formation of an electric field in the programmable resistance-based memory cell region 242. The electric field breaks down the dielectric structure of the programmable resistance-based memory cell region 242, resulting in a reduced electrical resistance in the programmable resistance-based memory cell region 242. The reduced electrical resistance may correspond to a second logic value. In some implementations, the dielectric breakdown in the programmable resistance-based memory cell region 242 may be reversable (e.g., non-permanent), enabling the non-volatile memory structure 208 to operate as an ReRAM structure (e.g., a programmable ReRAM cell). In some implementations, the dielectric breakdown in the programmable resistance-based memory cell region 242 may be permanent (e.g., non-reversable), enabling the non-volatile memory structure 208 to operate as a one-time programmable memory anti-fuse structure.
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The dielectric layers 302, 306, and 310 may each include one or more low dielectric constant (low-k) dielectric materials such as a silicon oxide (SiOx), fluoride-doped silicate glass (FSG), and/or another low-k dielectric material. The dielectric layers 304 and 308 may each include one or more high dielectric constant (high-k) dielectric materials to provide etch selectivity relative to the dielectric layers 302, 306, and 310. Examples of high-k dielectric materials include dielectric materials having a dielectric constant greater than the dielectric constant of silicon oxide (approximately 3.6), such as aluminum oxide (AlOx), silicon carbon nitride (SiCN), and/or silicon nitride (SixNy), among other examples.
The volatile memory structure 206 may be included in the back end dielectric layer(s) of the semiconductor device. The volatile memory structure 206 may include a DRAM memory structure and/or another type of volatile memory structure. The volatile memory structure 206 may include a transistor structure 312 and a capacitor structure 224. The capacitor structure 224 may be configured to selectively store an electrical charge corresponding to a logical value (e.g., a “1” value or a “0” value) stored by the volatile memory structure 206. The transistor structure 312 may be configured to selectively control access to the capacitor structure 224. For example, the transistor structure 312 may be activated to enable a charge to be provided to the capacitor structure 224 through the transistor structure 312. As another example, the transistor structure 312 may be deactivated to enable a charge to be stored in (e.g., to remain in) the capacitor structure 224. As another example, the transistor structure 312 may be activated to perform a “read” operation in which a charge stored in the capacitor structure 224 is discharged through the transistor structure 312 and measured.
The volatile memory structure 206 may be physically coupled and/or electrically coupled with a word line conductive structure 314 in the dielectric layer 302 below and/or under the transistor structure 312. The word line conductive structure 314 may also be referred to as an access line conductive structure, a select line conductive structure, an address line conductive structure, and/or a row line conductive structure, among other examples. The word line conductive structure 314 may be configured to selectively provide a voltage or current to a gate structure 210 of the transistor structure 312 for performing access operations associated with the volatile memory structure 206. The word line conductive structure 314 may include a trench, a via, metal line, a metallization layer, and/or another type of conductive structure. The word line conductive structure 314 may include one or more conductive materials, such as one or more metals, one or more metal alloys, and/or one or more other types of conductive materials. Examples include copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), gold (Au), and/or silver (Ag), among other examples.
The gate structure 210 of the transistor structure 312 may be located over and/or on the word line conductive structure 314. In particular, the gate structure 210 and the word line conductive structure 314 may be in direct physical contact such that a current or a voltage may be directly applied to the gate structure 210 from the word line conductive structure 314. The gate structure 210 may be included in the dielectric layers 304 and 306. The gate structure 210 may include one or more liner layers 316 between a gate electrode 318 of the gate structure 210 and the word line conductive structure 314. The gate electrode 318 may include polysilicon (e.g., polycrystalline silicon), one or more conductive materials, one or more high-k materials, and/or a combination thereof. The liner layer(s) 316 may include adhesion liners (e.g., liners that are included to promote adhesion between the gate electrode 318 and the dielectric layers 304 and 306), barrier layers (e.g., layers that are included to reduce or minimize diffusion of the material of the gate electrode 318 into the dielectric layers 304 and 306 and/or into the word line conductive structure 314), and/or another type of liner layers.
A gate dielectric layer 320 may be included over and/or on the gate structure 210. The gate dielectric layer 320 may be included in the dielectric layer 306. In some implementations, each transistor structure 312 includes a separate gate dielectric layer 320. In some implementations, two or more transistor structures 312 in the volatile memory array 202 share the same gate dielectric layer 320. In other words, a gate dielectric layer 320 may extend and/or span across gate structures 210 of a plurality of transistor structures 312. The gate dielectric layer 320 may include one or more dielectric materials, including high dielectric constant (high-k) materials such as hafnium silicate (HfOxSi), zirconium silicate (ZrSiOx), hafnium oxide (HfOx), and/or zirconium oxide (ZrOx), among other examples.
In some implementations, each transistor structure 312 may include a channel layer 212 over and/or on the gate dielectric layer 320. In some implementations, a channel layer 212 may extend across a plurality of gate structures 210 of a plurality of transistor structures 312 included in the volatile memory array 202. The channel layer 212 may include one or more semiconductor materials, such as silicon (Si), germanium (Ge), doped silicon, doped germanium, indium zinc oxide (InZnO), indium tin oxide (InSnO), indium oxide (InxOy such as In2O3), gallium oxide (GaxOy such as Ga2O3), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), aluminum zinc oxide (AlxOyZnz such as Al2O5Zn2), aluminum doped zinc oxide, titanium oxide (TiOx), III-V semiconductor materials, and/or combinations (e.g., alloys or stacked layers) of semiconductor materials, among other examples. This enables a conductive channel to be selectively formed in the channel layer 212 based on current or a voltage being applied to the gate structure 210.
Source/drain regions 214 and 216 may be included over and/or on the channel layer 212. The source/drain regions 214 and 216 may be electrically coupled with channel layer 212 such that current is selectively permitted to flow between the source/drain regions 214 and 216 through the channel layer 212. The source/drain regions 214 and 216 may each include one or more semiconductor materials, such as silicon (Si), germanium (Ge), doped silicon, and/or doped germanium, among other examples. In some implementations, the source/drain regions 214 and/or 216 may include one or more liner layers and a conductive material (or a semiconductive materials). The one or more liner layers may include a barrier liner included to prevent material migration from the conductive material into the surrounding dielectric layers, an adhesion layer included to promote adhesion between the conductive material and the surrounding dielectric layers, and/or another type of liner layer. Examples of conductive materials include copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), gold (Au), and/or silver (Ag), among other examples. Examples of liner layers include tantalum (Ta), tantalum nitride (TaN), indium oxide (InO), tungsten nitride (WN), titanium nitride (TiN), and/or another suitable liner layer, among other examples.
The source/drain regions 214 and 216 may be respectively coupled with interconnect structures. For example, the source/drain region 214 may be coupled with an interconnect structure 218 that is located over and/or on the source/drain region 214. The interconnect structure 218 may electrically couple the source/drain region 214 with the bit line conductive structure 222. The bit line conductive structure 222 may also be referred to as a column line conductive structure. The bit line conductive structure 222 may be located over and/or on the interconnect structure 218, and may be configured to selectively receive a current from the capacitor structure 224 or to provide a current to the capacitor structure 224 through the transistor structure 312.
As another example, the source/drain region 216 may be coupled with an interconnect structure 220 that is located over and/or on the source/drain region 216. In the diagram in
The interconnect structures 218 and 220, and the bit line conductive structure 222, may each include vias, plugs, trenches, dual damascene structures, and/or another type of conductive structures. The interconnect structures 218 and 220, and the bit line conductive structure 222, may each include one or more conductive materials, such as one or more metals, one or more metal alloys, and/or one or more other types of conductive materials. Examples include copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), gold (Au), and/or silver (Ag), among other examples. In some implementations, interconnect structures 218 and/or 220 may include one or more liner layers and the conductive material(s). The one or more liner layers may include a barrier liner included to prevent material migration from the conductive material(s) into the surrounding dielectric layers, an adhesion layer included to promote adhesion between the conductive material(s) and the surrounding dielectric layers, and/or another type of liner layer. Examples of liner layers include tantalum (Ta), tantalum nitride (TaN), indium oxide (InO), tungsten nitride (WN), titanium nitride (TiN), and/or another suitable liner layer, among other examples.
The capacitor structure 224 may include a deep trench capacitor structure (DTC structure) having a relatively high aspect ratio between the height of the capacitor structure 224 and a width or critical dimension (CD) of the capacitor structure 224. The capacitor structure 224 may include sidewalls 322 and a bottom surface 324 connecting the sidewalls 322. The capacitor structure 224 may be coupled with the interconnect structure 220 at the bottom surface 324 of the capacitor structure 224. The capacitor structure 224 may be located in the dielectric layers 308 and 310, with the bottom surface 324 of the capacitor structure 224 extending through the dielectric layer 308 such that the bottom surface 324 is located in the dielectric layer 308.
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A ground conductive structure 332 may be included over and/or on the capacitor structure 224. The ground conductive structure 332 may include vias, plugs, trenches, dual damascene structures, and/or another type of conductive structures. The ground conductive structure 332 may be configured as an electrical ground for the volatile memory structure 206. The ground conductive structure 332 may include one or more conductive materials, such as one or more metals, one or more metal alloys, and/or one or more other types of conductive materials. Examples include copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), gold (Au), and/or silver (Ag), among other examples.
For example, the charge 334 may be provided to the capacitor structure 224 from the bit line conductive structure 222 to write a logical value to the volatile memory structure 206. Here, the charge 334 traverses along the flow path 336 from the bit line conductive structure 222, through the interconnect structure 218, through the source/drain region 214, through the channel layer 212 of the transistor structure 312, through the source/drain region 216, and through the interconnect structure 220 to the capacitor structure 224. A current or a voltage may be applied to the gate structure 210 from the word line conductive structure 314 to enable the charge 334 to flow through the channel layer 212. Moreover, a voltage may be applied to the bit line conductive structure 222 such that the electrical potential on the conductive layer 326 is greater relative to the electrical potential on the conductive layer 330 (which is grounded to 0 volts) to facilitate charging of the capacitor structure 224 through the transistor structure 312.
To read from or erase the logical value stored by the volatile memory structure 206, a current or a voltage may be applied to the gate structure 210 from the word line conductive structure 314 to enable the charge 334 to flow through the channel layer 212. The voltage may be removed from the bit line conductive structure 222 such that the charge 334 flows from the capacitor structure 224 to the bit line conductive structure 222 along the flow path 336 through the transistor structure 312.
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The dielectric layers 402, 406, and 410 may each include one or more low dielectric constant (low-k) dielectric materials such as a silicon oxide (SiOx), fluoride-doped silicate glass (FSG), and/or another low-k dielectric material. The dielectric layers 404 and 408 may each include one or more high-k dielectric materials to provide etch selectivity relative to the dielectric layers 402, 406, and 410. Examples of high-k dielectric materials include dielectric materials having a dielectric constant greater than the dielectric constant of silicon oxide (approximately 3.6), such as aluminum oxide (AlOx), silicon carbon nitride (SiCN), and/or silicon nitride (SixNy), among other examples.
The non-volatile memory structure 208 may be included in the back end dielectric layer(s) of the semiconductor device. The non-volatile memory structure 208 may include an ReRAM memory structure, an OTP anti-fuse memory structure, and/or another type of non-volatile memory structure. The non-volatile memory structure 208 may include a transistor structure 412. The transistor structure 412 may be configured to selectively control electrical pulses (e.g., current pulses, voltage pulses) to a programmable resistance-based memory cell region 242 of the non-volatile memory structure 208. For example, the transistor structure 412 may be repeatedly cycled between an activated state and a deactivated state to enable a plurality of electrical pulses to be provided to through the transistor structure 412.
The non-volatile memory structure 208 may be physically coupled and/or electrically coupled with a word line conductive structure 414 in the dielectric layer 402 below and/or under the transistor structure 412. The word line conductive structure 414 may also be referred to as an access line conductive structure, an address line conductive structure, and/or a row line conductive structure, among other examples. The word line conductive structure 414 may be configured to selectively provide a voltage or current to a gate structure 226 of the transistor structure 412 for performing access operations associated with the non-volatile memory structure 208. The word line conductive structure 414 may include a trench, a via, metal line, a metallization layer, and/or another type of conductive structure. The word line conductive structure 414 may include one or more conductive materials, such as one or more metals, one or more metal alloys, and/or one or more other types of conductive materials. Examples include copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), gold (Au), and/or silver (Ag), among other examples.
The gate structure 226 of the transistor structure 412 may be located over and/or on the word line conductive structure 414. In particular, the gate structure 226 and the word line conductive structure 414 may be in direct physical contact such that a current or a voltage may be directly applied to the gate structure 226 from the word line conductive structure 414. The gate structure 226 may be included in the dielectric layers 404 and 406. The gate structure 226 may include one or more liner layers 416 between a gate electrode 418 of the gate structure 226 and the word line conductive structure 414. The gate electrode 418 may include polysilicon (e.g., polycrystalline silicon), one or more conductive materials, one or more high-k materials, and/or a combination thereof. The liner layer(s) 416 may include adhesion liners (e.g., liners that are included to promote adhesion between the gate electrode 418 and the dielectric layers 404 and 406), barrier layers (e.g., layers that are included to reduce or minimize diffusion of the material of the gate electrode 418 into the dielectric layers 404 and 406 and/or into the word line conductive structure 414), and/or another type of liner layers.
A gate dielectric layer 420 may be included over and/or on the gate structure 226. The gate dielectric layer 420 may be included in the dielectric layer 406. In some implementations, each transistor structure 412 includes a separate gate dielectric layer 420. In some implementations, two or more transistor structures 412 in the non-volatile memory array 204 share the same gate dielectric layer 420. In other words, a gate dielectric layer 420 may extend and/or span across gate structures 226 of a plurality of transistor structures 412. The gate dielectric layer 420 may include one or more dielectric materials, including high-k materials such as hafnium silicate (HfOxSi), zirconium silicate (ZrSiOx), hafnium oxide (HfOx), and/or zirconium oxide (ZrOx), among other examples.
In some implementations, each transistor structure 412 may include a channel layer 228 over and/or on the gate dielectric layer 420. In some implementations, a channel layer 228 may extend across a plurality of gate structures 226 of a plurality of transistor structures 412 included in the non-volatile memory array 204. The channel layer 228 may include one or more semiconductor materials, such as silicon (Si), germanium (Ge), doped silicon, doped germanium, indium zinc oxide (InZnO), indium tin oxide (InSnO), indium oxide (InxOy such as In2O3), gallium oxide (GaxOy such as Ga2O3), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), aluminum zinc oxide (AlxOyZnz such as Al2O5Zn2), aluminum doped zinc oxide, titanium oxide (TiOx), III-V semiconductor materials, and/or combinations (e.g., alloys or stacked layers) of semiconductor materials, among other examples. This enables a conductive channel to be selectively formed in the channel layer 228 based on current or a voltage being applied to the gate structure 210.
Source/drain regions 230 and 232 may be included over and/or on the channel layer 228. The source/drain regions 230 and 232 may be electrically coupled with channel layer 228 such that current is selectively permitted to flow between the source/drain regions 230 and 232 through the channel layer 228. The source/drain regions 230 and 232 may each include one or more semiconductor materials, such as silicon (Si), germanium (Ge), doped silicon, and/or doped germanium, among other examples. In some implementations, the source/drain regions 230 and/or 232 may include one or more liner layers and a conductive material (or a semiconductive materials). The one or more liner layers may include a barrier liner included to prevent material migration from the conductive material into the surrounding dielectric layers, an adhesion layer included to promote adhesion between the conductive material and the surrounding dielectric layers, and/or another type of liner layer. Examples of conductive materials include copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), gold (Au), and/or silver (Ag), among other examples. Examples of liner layers include tantalum (Ta), tantalum nitride (TaN), indium oxide (InO), tungsten nitride (WN), titanium nitride (TiN), and/or another suitable liner layer, among other examples.
The source/drain regions 230 and 232 may be respectively coupled with interconnect structures. For example, and as shown in
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In some implementations, interconnect structures 234 and/or 236 may include one or more liner layers and the conductive material(s). The one or more liner layers may include a barrier liner included to prevent material migration from the conductive material(s) into the surrounding dielectric layers, an adhesion layer included to promote adhesion between the conductive material(s) and the surrounding dielectric layers, and/or another type of liner layer. Examples of liner layers include tantalum (Ta), tantalum nitride (TaN), indium oxide (InO), tungsten nitride (WN), titanium nitride (TiN), and/or another suitable liner layer, among other examples.
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The lesser spacing between the interconnect structure 236 and the select line conductive structure 240 enables the portion of the dielectric layer 406 between the interconnect structure 236 and the select line conductive structure 240 to function as the programmable resistance-based memory cell region 242. In some implementations, a distance or spacing between the interconnect structure 236 and the select line conductive structure 240 is included in a range of approximately 3 nanometers to approximately 15 nanometers. Forming the interconnect structure 236 and the select line conductive structure 240 such that the spacing between the interconnect structure 236 and the select line conductive structure 240 is included in this range provides sufficient electrical resistance between the interconnect structure 236 and the select line conductive structure 240 while still enabling the programmable resistance-based memory cell region 242 to be selectively programmed to form a conductive path between the interconnect structure 236 and the select line conductive structure 240 through the programmable resistance-based memory cell region 242 when the programmable resistance-based memory cell region 242 is in a programmed state. If the spacing between the interconnect structure 236 and the select line conductive structure 240 is outside of this range, process variations in forming the interconnect structure 236 and the select line conductive structure 240 may result in electrical shorting between the interconnect structure 236 and the select line conductive structure 240 if the distance is too small, whereas a greater power consumption and/or circuit design complexity for the non-volatile memory array 204 may result if the distance is too large (e.g., because of the higher breakdown voltage needed to modify the electrical resistance in the programmable resistance-based memory cell region 242). However, other values for the range are within the scope of the present disclosure. In some implementations, the spacing between the interconnect structure 236 and the select line conductive structure 240 may be selected based on one or more parameters for the non-volatile memory structure 208, such as the semiconductor processing node used to manufacture the non-volatile memory structure 208, a target breakdown voltage for the non-volatile memory structure 208, a device pitch for the non-volatile memory structure 208, an operating voltage for the non-volatile memory structure 208, and/or another parameter.
The interconnect structures 234 and 236, the bit line conductive structure 238, and the select line conductive structure 240, may each include vias, plugs, trenches, dual damascene structures, and/or another type of conductive structures. The interconnect structures 234 and 236, the bit line conductive structure 238, and the select line conductive structure 240, may each include one or more conductive materials, such as one or more metals, one or more metal alloys, and/or one or more other types of conductive materials. Examples include copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), gold (Au), and/or silver (Ag), among other examples.
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In some implementations, the magnitude of the electrical pulse 422 (e.g., referred to as the breakdown voltage) may be selected to enable the dielectric breakdown in the programmable resistance-based memory cell region 242 to be either reversable or permanent. Higher breakdown voltages may be used to achieve a greater amount of dielectric breakdown in the programmable resistance-based memory cell region 242, and therefore may be used to implement one-time programmable anti-fuse operation in the non-volatile memory structure 208 (e.g., such that the non-volatile memory structure 208 is configured to be programmed for a single programming operation). Lower breakdown voltages may be used to achieve a lesser amount of dielectric breakdown in the programmable resistance-based memory cell region 242, and therefore may be used to implement ReRAM operation in the non-volatile memory structure 208 (which enables the non-volatile memory structure 208 to be repeatedly programmed and erased in a plurality of program-erase cycles).
To read from the non-volatile memory structure 206, a current or a voltage may be applied to the gate structure 226 from the word line conductive structure 414 to enable an electrical current to flow through the channel layer from the bit line conductive structure 238, through the channel layer 228, through the programmable resistance-based memory cell region 242, and to the select line conductive structure 240. The electrical current may be measured to determine a voltage drop across the programmable resistance-based memory cell region 242, which may be based on the electrical resistance of the programmable resistance-based memory cell region 242. A high electrical resistance may correspond to a first logic value (e.g., a “0” value or a “1” value) stored by the non-volatile memory structure 208, whereas a low electrical resistance may correspond to a second logic value stored by the non-volatile memory structure 208.
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The deposition tool 102 and/or the plating tool 112 may deposit the word line conductive structure 314 in the recess using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
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In some implementations, a pattern in a photoresist layer is used to form the channel layer 212 and the gate dielectric layer 320. In these implementations, the deposition tool 102 forms the photoresist layer on the dielectric layer 508. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches through the dielectric layer 508, through the channel material layer 506, and/or through the dielectric layer 504 based on the pattern. The remaining portions of the channel material layer 506 over the gate structure 210 corresponds to the channel layer 212, and remaining portions of the dielectric layer 504 over the gate structure 210 correspond to the gate dielectric layer 320. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the channel layer 212 and the gate dielectric layer 320 based on a pattern.
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In some implementations, a pattern in a photoresist layer is used to form a recess in the dielectric layer 306 over and to the source/drain region 214. In these implementations, the deposition tool 102 forms the photoresist layer on the dielectric layer 306. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches into the dielectric layer 306 based on the pattern to form the recess. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the recesses based on a pattern.
The deposition tool 102 and/or the plating tool 112 may deposit the interconnect structure 218 in the recess using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
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In some implementations, a pattern in a photoresist layer is used to form a recess in the dielectric layer 306. In these implementations, the deposition tool 102 forms the photoresist layer on the dielectric layer 306. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches into the dielectric layer 306 based on the pattern to form the recess. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the recess based on a pattern.
The deposition tool 102 and/or the plating tool 112 may deposit the bit line conductive structure 222 in the recess using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
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In some implementations, a pattern in a photoresist layer is used to form a recess in the dielectric layer 306 over and to the source/drain region 216 such that the source/drain region 216 is exposed through the recess. In these implementations, the deposition tool 102 forms the photoresist layer on the dielectric layer 306. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches into the dielectric layer 306 based on the pattern to form the recess. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the recess based on a pattern.
The deposition tool 102 and/or the plating tool 112 may deposit the interconnect structure 220 in the recess using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
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In some implementations, a pattern in a photoresist layer is used to form a recess in the dielectric layers 308 and/or 310 over and to the interconnect structure 220. In these implementations, the deposition tool 102 forms the photoresist layer on the dielectric layer 310. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches into the dielectric layers 308 and 310 based on the pattern to form the recess. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the recess based on a pattern.
The deposition tool 102 and/or the plating tool 112 may deposit the conductive layer 326, the dielectric layer 328, and the conductive layer 330 in the recesses using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
Additional dielectric material may be deposited for the dielectric layer 310 after formation of the capacitor structure 224. The deposition tool 102 may deposit the additional dielectric material using a CVD technique, a PVD technique, an ALD technique, another deposition technique described above in connection with
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In some implementations, a pattern in a photoresist layer is used to form a recess in the dielectric layer 310. In these implementations, the deposition tool 102 forms the photoresist layer on the dielectric layer 310. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches into the dielectric layer 310 based on the pattern to form the recess. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the recess based on a pattern.
The deposition tool 102 and/or the plating tool 112 may deposit the ground conductive structure 332 in the recess using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
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The deposition tool 102 and/or the plating tool 112 may deposit the word line conductive structure 414 in the recess using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
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In some implementations, a pattern in a photoresist layer is used to form the channel layer 228 and the gate dielectric layer 420. In these implementations, the deposition tool 102 forms the photoresist layer on the dielectric layer 608. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches through the dielectric layer 608, through the channel material layer 606, and/or through the dielectric layer 604 based on the pattern. The remaining portions of the channel material layer 606 over the gate structure 226 corresponds to the channel layer 228, and remaining portions of the dielectric layer 604 over the gate structure 226 correspond to the gate dielectric layer 420. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the channel layer 228 and the gate dielectric layer 420 based on a pattern.
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In some implementations, a pattern in a photoresist layer is used to form a recess in the dielectric layer 406 over and to the source/drain region 230. In these implementations, the deposition tool 102 forms the photoresist layer on the dielectric layer 406. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches into the dielectric layer 406 based on the pattern to form the recess. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the recesses based on a pattern.
The deposition tool 102 and/or the plating tool 112 may deposit the interconnect structure 234 in the recess using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
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In some implementations, a pattern in a photoresist layer is used to form a recess in the dielectric layer 406. In these implementations, the deposition tool 102 forms the photoresist layer on the dielectric layer 406. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches into the dielectric layer 406 based on the pattern to form the recesses. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the recess based on a pattern.
The deposition tool 102 and/or the plating tool 112 may deposit the bit line conductive structure 238 in a recess using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
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In some implementations, a pattern in a photoresist layer is used to form the recess 612 in the dielectric layer 406 over and to the source/drain region 232. In these implementations, the deposition tool 102 forms the photoresist layer on the dielectric layer 406. The exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. The developer tool 106 develops and removes portions of the photoresist layer to expose the pattern. The etch tool 108 etches into the dielectric layer 406 based on the pattern to form the recess 612. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique. In some implementations, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and/or another technique). In some implementations, a hard mask layer is used as an alternative technique for forming the recess 612 based on a pattern.
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The deposition tool 102 and/or the plating tool 112 may deposit the interconnect structure 236 in the recess 612 using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, another deposition technique described above in connection with
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The semiconductor device 700 includes one or more stacked layers, including a dielectric layer 706, an etch stop layer (ESL) 708, a dielectric layer 710, an ESL 712, a dielectric layer 714, an ESL 716, a dielectric layer 718, an ESL 720, a dielectric layer 722, an ESL 724, and a dielectric layer 726, among other examples. The dielectric layers 706, 710, 714, 718, 722, and 726 are included to electrically isolate various structures of the semiconductor device 700. The dielectric layers 706, 710, 714, 718, 722, and 726 include a silicon nitride (SixNy), an oxide (e.g., a silicon oxide (SiOx) and/or another oxide material), and/or another type of dielectric material. The ESLs 708, 712, 716, 720, 724 includes a layer of material that is configured to permit various portions of the semiconductor device 700 (or the layers included therein) to be selectively etched or protected from etching to form one or more of the structures included in the semiconductor device 700.
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The epitaxial regions 728 are electrically connected to metal source or drain contacts 730 of the transistors included in the semiconductor device 700. The metal source or drain contacts (MDs or CAs) 730 include cobalt (Co), ruthenium (Ru), and/or another conductive or metal material. The transistors further include gates 732 (MGs), which are formed of a polysilicon material, a metal (e.g., tungsten (W) or another metal), and/or another type of conductive material. The metal source or drain contacts 730 and the gates 732 are electrically isolated by one or more sidewall spacers, including spacers 734 on each side of the metal source or drain contacts 730 and spacers 736 on each side of the gate 732. The spacers 734 and 736 include a silicon oxide (SiOx), a silicon nitride (SixNy), a silicon oxy carbide (SiOC), a silicon oxycarbonitride (SiOCN), and/or another suitable material. In some implementations, the spacers 734 are omitted from the sidewalls of the source or drain contacts 730.
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The metal source or drain contacts 730 are electrically connected to source or drain interconnects 738 (e.g., source/drain vias or VDs). One or more of the gates 732 are electrically connected to gate interconnects 740 (e.g., gate vias or VGs). The interconnects 738 and 740 include a conductive material such as tungsten, cobalt, ruthenium, copper, and/or another type of conductive material. In some implementations, the gates 732 are electrically connected to the gate interconnects 740 by gate contacts 742 (CB or MP) to reduce contact resistance between the gates 732 and the gate interconnects 740. The gate contacts 742 include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu) or gold (Au), among other examples of conductive materials.
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One or more memory arrays (e.g., a volatile memory array 202, a non-volatile memory array 204) may be included in one or more layers in the BEOL region of the semiconductor device 700. In some implementations, a plurality of volatile memory structures 206 of a volatile memory array 202 and/or a plurality of non-volatile memory structures 208 of a non-volatile memory array 204 may be included in the dielectric layer 714 the dielectric layer 718, the dielectric layer 722, and/or the ESL 724, among other examples. The volatile memory structures 206 may be configured for caching and other volatile memory functions in the semiconductor device 700, whereas the non-volatile memory structures 208 may be configured for long-term storage, firmware storage, circuit trim parameter storage, and/or other non-volatile memory functions in the semiconductor device 700. In some implementations, volatile memory structures 206 and the non-volatile memory structures 208 may be formed in the same set of semiconductor processing operations or a subset of the same semiconductor processing operations to reduce complexity of manufacturing the semiconductor device 700.
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The bus 810 may include one or more components that enable wired and/or wireless communication among the components of the device 800. The bus 810 may couple together two or more components of
The memory 830 may include volatile and/or nonvolatile memory. For example, the memory 830 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory). The memory 830 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and/or removable memory (e.g., removable via a universal serial bus connection). The memory 830 may be a non-transitory computer-readable medium. The memory 830 may store information, one or more instructions, and/or software (e.g., one or more software applications) related to the operation of the device 800. In some implementations, the memory 830 may include one or more memories that are coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 820), such as via the bus 810. Communicative coupling between a processor 820 and a memory 830 may enable the processor 820 to read and/or process information stored in the memory 830 and/or to store information in the memory 830.
The input component 840 may enable the device 800 to receive input, such as user input and/or sensed input. For example, the input component 840 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and/or an actuator. The output component 850 may enable the device 800 to provide output, such as via a display, a speaker, and/or a light-emitting diode. The communication component 860 may enable the device 800 to communicate with other devices via a wired connection and/or a wireless connection. For example, the communication component 860 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.
The device 800 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 830) may store a set of instructions (e.g., one or more instructions or code) for execution by the processor 820. The processor 820 may execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions, by one or more processors 820, causes the one or more processors 820 and/or the device 800 to perform one or more operations or processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more operations or processes described herein. Additionally, or alternatively, the processor 820 may be configured to perform one or more operations or processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.
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Process 900 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.
In a first implementation, process 900 includes forming a gate dielectric layer 420 of the non-volatile memory structure 208 over the gate structure 226, and forming a channel layer 228 of the non-volatile memory structure 208 over the gate dielectric layer 420, where forming the first source/drain region 230 and the second source/drain region 232 includes forming the first source/drain region 230 and the second source/drain region 232 over the channel layer 228.
In a second implementation, alone or in combination with the first implementation, forming the second interconnect structure 236 includes forming the second interconnect structure 236 after forming the bit line conductive structure 238 and after forming the select line conductive structure 240.
In a third implementation, alone or in combination with one or more of the first and second implementations, forming the second interconnect structure 236 includes forming the second interconnect structure 236 between the bit line conductive structure 238 and the select line conductive structure 240.
In a fourth implementation, alone or in combination with one or more of the first through third implementations, process 900 includes forming a gate structure 210, of a volatile memory structure 206 of the semiconductor device, in the plurality of BEOL dielectric layers, where the gate structure 226 of the non-volatile memory structure 208 and the gate structure 210 of the volatile memory structure 206 are formed in a same set of semiconductor processing operations.
In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, process 900 includes forming a first source/drain region 214 and a second source/drain region 216 of a volatile memory structure 206 of the semiconductor device, where the first source/drain region 230 and the second source/drain region 232 of the non-volatile memory structure 208 and the first source/drain region 214 and the second source/drain region 216 of the volatile memory structure are formed in a same set of first semiconductor processing operations, forming a first interconnect structure 218 for the non-volatile memory structure on the first source/drain region 214 of the volatile memory structure 206, where the first interconnect structure 234 of the non-volatile memory structure 208 and the first interconnect structure 218 of the volatile memory structure 206 are formed in a same set of second semiconductor processing operations, and forming a second interconnect structure 220 for the volatile memory structure 206 on the second source/drain region 216 of the volatile memory structure 206, where the second interconnect structure 236 of the non-volatile memory structure 208 and the second interconnect structure 220 of the volatile memory structure 206 are formed in a same set of third semiconductor processing operations.
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In this way, a semiconductor device may include a non-volatile memory structure that may be formed in a BEOL region of a semiconductor device. The non-volatile memory structure may include a dielectric-based OTP anti-fuse memory structure or a dielectric-based ReRAM, among other examples. The non-volatile memory structure may be selectively programmed based on modifying an electrical resistance of the non-volatile memory structure, and may retain data stored in the non-volatile memory structure even when electrical power is removed from the semiconductor device.
As described in greater detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a plurality of back end dielectric layers. The semiconductor device includes a non-volatile memory structure included in the plurality of back end dielectric layers, comprising, a gate structure a channel layer over the gate structure a first source/drain region and a second source/drain region over the channel layer a first interconnect structure above and coupled with the first source/drain region, where the first interconnect structure is coupled with a bit line conductive structure in the semiconductor device a second interconnect structure above and coupled with the second source/drain region, where the second interconnect structure is adjacent to a select line conductive structure in the semiconductor device, and where a portion of a back end dielectric layer, of the plurality of back end dielectric layers, is located between the second interconnect structure and the select line conductive structure.
As described in greater detail above, some implementations described herein provide a method. The method includes forming a word line conductive structure in a semiconductor device. The method includes forming a plurality of BEOL dielectric layers over the word line conductive structure. The method includes forming, over the word line conductive structure, a recess through the plurality of BEOL dielectric layers to expose the word line conductive structure through the recess. The method includes forming a gate structure, of a non-volatile memory structure of the semiconductor device, in the recess such that the gate structure is coupled with the word line conductive structure. The method includes forming a first source/drain region and a second source/drain region of the non-volatile memory structure over the gate structure. The method includes forming a first interconnect structure on the first source/drain region. The method includes forming a bit line conductive structure over the first interconnect structure such that the bit line conductive structure is physically coupled with the first interconnect structure, where the bit line conductive structure is formed in a BEOL dielectric layer of the plurality of BEOL dielectric layers. The method includes forming a select line conductive structure in the BEOL dielectric layer. The method includes forming a second interconnect structure in the BEOL dielectric layer and on the second source/drain region, where the second interconnect structure is formed such that the second interconnect structure and the select line conductive structure are spaced apart by the BEOL dielectric layer.
As described in greater detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a plurality of back end dielectric layers. The semiconductor device includes a volatile memory array, in the plurality of back end dielectric layers, comprising a plurality of volatile memory structures. The semiconductor device includes a non-volatile memory array, in the plurality of back end dielectric layers, comprising a plurality of non-volatile memory structures, where a non-volatile memory structure, of the plurality of non-volatile memory structures, includes a programmable resistance-based memory cell region that corresponds to a portion of a back end dielectric layer of the plurality of back end dielectric layers.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
