Patent Application
20240266409
The present application generally relates to manufacturing of semiconductor integrated circuits. More particularly, it relates to method of forming backside contact of semiconductor transistors and structures formed thereby.
With the increased demand for high density of semiconductor integrated circuitry, power supplies and some signal routing functionalities are being moved to the backside of the semiconductor chip or wafer for better usage of the real estate at the frontside. In the process of making backside source/drain contact, a placeholder dummy material is usually first formed in the source/drain region during a process of forming front-end-of-line (FEOL) structures. The dummy material is subsequently removed, when the process is moved to the backside of the semiconductor wafer to form power supplies, and replaced with some type of conductive or metal material to form backside source/drain contacts.
Currently, the dummy material used as placeholder is usually silicon-germanium (SiGe) and the placeholder may be formed through an epitaxial growth process. However, source/drain epitaxial regions of the semiconductor transistors are usually formed immediately above and next to the SiGe placeholder. Because of the proximity, the removal process of the placeholder, when being processed from the backside of the semiconductor wafer, has been found difficult without causing structural damage to the source/drain regions of the transistor, to which the backside source/drain contacts are supposed to provide power supplies.
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a backside source/drain contact, where a central portion of the backside source/drain contact extends further, than a side portion of the backside source/drain contact, into a source/drain region of a first transistor and a second transistor. By extending into the source/drain region of the first and second transistors, the backside source/drain contact is effectively placed closer to the silicon channels of the first and second transistors thereby reducing or lowering the transfer resistance from the source/drain contacts to the silicon channels.
In one embodiment, the backside source/drain contact includes an upper portion; a middle portion; and a bottom portion, and the upper portion of the backside source/drain contact has a diamond shape and situates horizontally between the first transistor and the second transistor. The diamond shape of the upper portion of the backside source/drain contact brings the backside source/drain contact closer to the silicon channels of the first and second transistors.
In another embodiment, the middle portion of the backside source/drain contact is at least partially embedded in a substrate and a sidewall of the middle portion of the backside source/drain contact is surrounded by a dielectric liner.
In yet another embodiment, the first and second transistors are nanosheet transistors formed on top of the substrate and share the source/drain region, and where the source/drain region saddles on top of the upper portion of the backside source/drain contact.
In one embodiment, at least the first transistor is a nanosheet transistor having a set of nanosheets, and the central portion of the backside source/drain contact has a height that is higher than a bottom surface of a bottom-most nanosheet of the set of nanosheets.
Embodiments of present invention also provide a method of forming backside source/drain contact. The method includes forming a dummy contact structure in a substrate, the dummy contact structure having a central portion and a side portion, the central portion being higher than the side portion to have a height above the substrate; forming a source/drain region of a first transistor and a second transistor above the dummy contact structure, the first and second transistors being above the substrate; removing the dummy contact structure from a backside of the substrate to create a backside contact opening; and forming a backside source/drain contact by filling the backside contact opening with a conductive material. With the dummy contact structure having a central portion that is higher than a side portion and above the substrate, the later resulting backside source/drain contact may be made closer to the channel or channel regions of the first and second transistors. The closer distance in-turn reduces or lowers a transfer resistance between the backside source/drain contact and the channels of the first and second transistors.
In one embodiment, forming the dummy contact structure includes creating a dummy contact opening in the substrate; forming a dielectric liner lining a sidewall of the dummy contact opening; and epitaxially growing the dummy contact structure from the substrate at a bottom of the dummy contact opening such that an upper portion of the dummy contact structure has a diamond shape.
In another embodiment, forming the backside source/drain contact includes forming the backside source/drain contact to have an upper portion; a middle portion; and a bottom portion, where the upper portion of the backside source/drain contact has the diamond shape of the dummy contact structure. The diamond shape of the upper portion of the backside source/drain contact brings the backside source/drain contact closer to the channel regions of the transistors thereby lowering or reducing a transfer resistance between the backside source/drain contact and the channel regions of the transistors.
According to one embodiment, the method further includes, before forming the source/drain region, oxidizing a top surface of the dummy contact structure to form an etch-stop layer, where removing the dummy contact structure from the backside of the substrate includes selectively removing the dummy contact structure relative to the etch-stop layer. The use of the etch-stop layer helps prevent causing damages to the source/drain region during the process of removing the dummy contact structure, thereby resulting in a smooth bottom surface of the source/drain region.
According to another embodiment, the method further includes, after removing the dummy contact structure, selectively removing the etch-stop layer relative to the source/drain region, thereby creating the backside contact opening having a shape that is similar to the diamond shape of the dummy contact structure.
The present invention will be understood and appreciated more fully from the following detailed description of embodiments of present invention, taken in conjunction with accompanying drawings of which:
It will be appreciated that for simplicity and clarity purpose, elements shown in the drawings have not necessarily been drawn to scale. Further, and if applicable, in various functional block diagrams, two connected devices and/or elements may not necessarily be illustrated as being connected. In some other instances, grouping of certain elements in a functional block diagram may be solely for the purpose of description and may not necessarily imply that they are in a single physical entity, or they are embodied in a single physical entity.
In the below detailed description and the accompanying drawings, it is to be understood that various layers, structures, and regions shown in the drawings are both demonstrative and schematic illustrations thereof that are not drawn to scale. In addition, for the ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present such as, by way of example only, 1% or less than the stated amount. Likewise, the terms “on”, “over”, or “on top of” that are used herein to describe a positional relationship between two layers or structures are intended to be broadly construed and should not be interpreted as precluding the presence of one or more intervening layers or structures.
To provide spatial context to different structural orientations of the semiconductor structures shown in the drawings, XYZ Cartesian coordinates may be provided in some of the drawings. The terms “vertical” or “vertical direction” or “vertical height” as used herein denote a Z-direction of the Cartesian coordinates shown in the drawings, and the terms “horizontal” or “horizontal direction” or “lateral direction” as used herein denote an X-direction and/or a Y-direction of the Cartesian coordinates shown in the drawings.
Moreover, although various reference numerals may be used across different drawings, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus detailed explanations of the same or similar features, elements, or structures may not be repeated for each of the drawings for economy of description. Labelling for the same or similar elements in some drawings may be omitted as well in order not to overcrowd the drawings.
More specifically, the transistor 210 may be formed on top of the substrate 101, via a bottom dielectric isolation (BDI) such as a dielectric layer 102, to include a first set of nanosheets 211 separated by a first set of dummy sheets 212. The nanosheets 211 may be silicon (Si) or silicon-germanium (SiGe) of a first SiGe concentration level, and the dummy sheets 212 may be SiGe of a second SiGe concentration level. The use of different SiGe concentration levels enables a selective etching process of the dummy sheets 212 relative to the nanosheets 211. Indentations 213 may be formed at a left side and a right side of the dummy sheets 212. A dummy gate 311 may be formed on top of the nanosheets 211. The dummy gate 311 may be covered by a hard mask 312 with sidewall spacers 313 at a left and a right sidewall thereof.
Similar to the transistor 210, the transistor 220 may be formed to include a second set of nanosheets 221 separated by a second set of dummy sheets 222. Indentations 223 may be formed at a left side and a right side of the dummy sheets 222. A dummy gate 321 may be formed on top of the nanosheet 221, which is covered by a hard mask 322 with sidewall spacers 323 at a left and a right sidewall thereof.
In the process of forming the transistors 210 and 220, a source/drain (S/D) recess 201 may be formed between the first set of nanosheets 211 and the second set of nanosheets 221. Embodiments of present invention further provide forming a dielectric liner 401 such as a silicon-nitride (SiN) liner lining, in the S/D recess 201, sidewalls of the first set of nanosheets 211 and the second set of nanosheets 221 and a top surface of an exposed portion of the dielectric layer 102 above the substrate 101.
After removing the horizontal portion of the dielectric liner 401 above the dielectric layer 102, embodiments of present invention provide further etching through the exposed dielectric layer 102 and subsequently etching the underneath substrate 101 thereby creating a dummy contact opening 202 in the dielectric layer 102 and the substrate 101 for forming a dummy contact structure.
In one embodiment, the dielectric liner 403 of SiCN, SiOCN, or SiBCN is materially different from that of the dielectric liner 402, which may be for example SiN, and is also materially different from the etch-stop layer 502 (see
Embodiments of present invention further provide performing an oxidation process to oxidize the exposed top surface of the dummy contact structure 501 to form an etch-stop layer 502, such as an oxide layer, covering the diamond shaped dummy contact structure 501. For example, the oxidation process may be performed in an environment containing oxygen at an elevated temperature ranging from about 700 Celsius (C) to about 1200 C and for a duration of 180 to 600 seconds, and the etch-stop layer 502 so created may have a thickness around 2˜7 nm. The etch-stop layer 502 helps enabling a selective etching process, which in-turn helps the removing of the dummy contact structure 501 later, without causing damage to a source/drain region formed above the etch-stop layer 502.
Embodiments of present invention provide further forming a dielectric layer 601 above the first set and the second set of nanosheets 211 and 221 of the first and the second transistor 210 and 220, including above the source/drain region 503; and forming a back-end-of-line (BEOL) structure 602, above the dielectric layer 601, which includes one or more metal levels for device powering and signal routing. A carrier wafer 701 is then bonded onto the BEOL structure 602 such that the semiconductor structure 10 may be flipped upside-down for further processing from a backside of the semiconductor substrate 101.
More particularly, following the step illustrated in
For example, the upper portion of the backside contact opening 802 has a pointy center. The pointy center or central portion 8021 of the backside contact opening 802 may have a height H2 that is higher than a height of a side portion 8022 of the backside contact opening 802. For example, the height H2 of the central portion 8021 of the backside contact opening 802 may be between a top surface of the dielectric layer 102 and a top surface of a bottom-most nanosheet of the first set of nanosheets 211 or the second set of nanosheets 221. In one embodiment, the pointy center or central portion 8021 of the backside contact opening 802 may have a height H2 that is higher than a bottom surface of a bottom-most nanosheet of the first set of nanosheets 211 or the second set of nanosheets 221.
It is to be understood that the exemplary methods discussed herein may be readily incorporated with other semiconductor processing flows, semiconductor devices, and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Accordingly, at least portions of one or more of the semiconductor structures described herein may be implemented in integrated circuits. The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other high-level carrier) or in a multichip package (such as a ceramic carrier that has surface interconnections and/or buried interconnections). In any case the chip may then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product, such as a motherboard, or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions above have been presented for the purposes of illustration of various embodiments of present invention and they are not intended to be exhaustive and present invention are not limited to the embodiments disclosed. The terminology used herein was chosen to best explain the principles of the embodiments, practical application or technical improvement over technologies found in the marketplace, and to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. Such changes, modification, and/or alternative embodiments may be made without departing from the spirit of present invention and are hereby all contemplated and considered within the scope of present invention. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the spirit of the invention.
