(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating copper damascene and dual damascene interconnects whereby negative effects of exposure of the copper surface are negated.
(2) Description of the Prior Art
In the creation of semiconductor devices, an important aspect of this creation is the interconnect metal that is provided between elements of semiconductor devices. Interconnect metal typically comprises metal conductive lines and vias that provide the interconnection of integrated circuits in semiconductor devices and/or the interconnections in a multilayer substrate over the surface of which semiconductor devices are mounted. One of the processes that is frequently used for the creation of conductive interconnects is the damascene and the dual damascene process. In fabricating Very and Ultra Large Scale Integration (VLSI and ULSI) circuits with the dual damascene process, a layer of insulating or dielectric material, comprising for instance silicon oxide, is patterned with several thousand openings. These openings form the pattern for the conductive lines and vias, which are filled at the same time with metal, such as typically aluminum but more recently copper. The pattern of conductive lines and vias serves to interconnect active and passive elements of an integrated circuit. The dual damascene process also is used to form multilevel conductive lines of metal, such as copper, in layers of insulating material, such as polyimide, using therewith multi-layer substrates over the surface of which semiconductor devices are mounted.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of the single damascene process, conductive via openings also are formed. In the standard dual damascene process, the insulating layer is coated with a layer of photoresist. The coated layer of photoresist is first exposed through a first mask with an image pattern of the via openings, the via pattern is anisotropically etched in the upper half of the insulating layer. The photoresist now is second exposed through a second mask with an image pattern of conductive lines after the second exposure has been aligned with the first exposure pattern in order to encompass the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings that are previously created in the upper half of the insulating layer are simultaneously etched and replicated in the lower half of the insulating material. After the etching is complete, both the vias and line openings are filled with metal.
The dual damascene process is an improvement over the single damascene process since the dual damascene process permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating processing steps. Although the standard damascene process offers a number of advantages over other processes for forming interconnections, it has a number of disadvantages. For instance, the dual damascene process requires two masking steps to form the pattern, a first mask for the vias and a second mask for the conductive lines. Further, the edges of the via openings in the lower half of the insulating layer, after the second etching, tend to be poorly defined because of the two etchings. In addition, since alignment of the two masks is critical in order for the pattern for the conductive lines to be over the pattern of the vias, a relatively large tolerance is provided resulting in via openings that do not extend the full width of the conductive line.
Copper is gaining increased use as an interconnect metal due to its relatively low cost and low resistivity. Copper however has a relatively large diffusion coefficient into a surrounding dielectric material such as silicon dioxide and silicon. Copper, which is used as an interconnect medium, therefore readily diffuses into the silicon dioxide layer causing the dielectric to become conductive and decreasing the dielectric strength of the silicon dioxide layer. Copper interconnects are therefore typically encapsulated by at least one diffusion barrier to prevent diffusion into the silicon dioxide layer. Copper further is well known to be very sensitive to surface exposure, most typically resulting in oxidation of the exposed copper surface.
The invention addresses concerns of creating copper interconnects and, more specifically, the negative impacts that are incurred by an exposed surface of copper interconnects.
U.S. Pat. No. 6,143,641 (Kitch) shows a dual damascene with cap layers.
U.S. Pat. No. 6,350,675 B1 (Chooi et al.) shows a dual damascene process with barrier layers.
U.S. Pat. No. 6,281,127 B1 (Shue) shows a self-passivation process for a dual damascene interconnect.
U.S. Pat. No. 6,274,499 (Gupta et al.) shows a cap over an interconnect.
U.S. Pat. No. 6,258,713 B1 (Yu et al.) discloses a dual damascene with a cap.
A principle objective of the invention is to provide a method of creating damascene types copper interconnects whereby negative effects of surface exposure during the process of creating these interconnects are negated.
Another objective of the invention is to provide a method of creating copper damascene interconnects whereby the negative impact of in-line exposure to processing chemicals such as etching chemicals is negated.
Yet another objective of the invention is to provide a method of creating copper damascene interconnects whereby effects of copper back-sputtering are negated.
A still further objective of the invention is to provide a method of creating copper damascene interconnects whereby formation of copper surface irregularities such as copper hillocks is prevented.
In accordance with the objectives of the invention a new method is provided for the creation of damascene copper interconnects. A method is provided whereby created copper surfaces are capped with a layer of barrier material. With the cap structure of barrier material, the surface of the created copper interconnect is shielded against outside influences such as effects of processing chemicals. As a result of the creation Of a cap of barrier material, conventional concerns of copper oxidation, copper back sputtering and the like are eliminated.
The creation of semiconductor devices having sub-micron and deep submicron device feature size has resulted in the conventional interconnect medium of aluminum being progressively replaced by copper or copper alloys including aluminum-copper (AlCu). For the creation of conductive interconnects, the single and dual damascene processes are frequently used for this purpose.
Applying state-of-the-art methods of creating single and dual damascene interconnects, the copper that is used as the conductive interconnect medium is readily exposed during processing to the fabrication environment, which in most applications comprises processing chemicals such as etchants.
As a result of this exposure of the copper surface, the copper reacts with the exposing substance, a reaction that has a negative impact on the exposed copper surface. In addition, this interaction between the copper and the environmentally present processing chemicals readily results in copper back-sputtering, causing the in this manner disbursed copper to be deposited on and to adhere to sidewalls of openings that have been created through layers of surrounding dielectric. This latter phenomenon results in degrading of the electrical performance of the created conductive interconnects since the surface between the surrounding dielectric and the deposited interconnect metal of copper is poorly defined. In addition, interaction between surrounding chemicals, for instance applied during a processing step of Chemical Vapor Deposition (CVD), readily leads to the formation of hillocks or surface irregularities in the exposed copper surface.
Copper is well known to readily oxidize when exposed to an oxygen containing environment such as air, to then remove the formed layer of copper oxide such steps as post-etch cleaning or pre-metallization treatment are frequently applied. These steps however do not assure that residual copper, that has formed over sidewalls of created via and trench openings, is also removed. In addition, the conventional step of pre-metallization treatment may further aggravate the situation by causing copper back sputtering.
To prevent all of the above highlighted negative aspects of creating single damascene and dual damascene copper interconnects, the invention provides for the creation of a cap layer of barrier material, as will now be explained in detail using
Referring first specifically to the cross section that is shown in
It must be noted in the cross section that is shown in
A conventional layer 15 of barrier material has been deposited over sidewalls of openings created for the deposition of copper vias and interconnect lines 13 through the first layer 14 of etch stop material and second layer 16 of dielectric. The copper interconnects 13 may first, at a lower level, comprise vias created through the layer 14 of etch stop material after which interconnect trenches are created through the second layer 16 of IMD, the trenches being filled with copper.
Conventional processing may also be applied to remove all or part of the barrier layer 15 from the bottom of the openings created through the layers 14 and 16 of dielectric, this in order to improve contact resistance of the created copper interconnects 13. Since this is not germane to the invention, this aspect has not been highlighted in the cross section shown in
Barrier layer is formed of a material selected from the group consisting of without however being limited thereto tungsten, Ti/TiN:W (titanium/titanium nitride:tungsten), titanium-tungsten/titanium or titanium-tungsten nitride/titanium or titanium nitride or titanium nitride/titanium, tantalum, tantalum nitride, tantalum silicon nitride, niobium, molybdenum, aluminum, aluminum oxide (AlxOy).
As a material for the layer 18 of barrier material is selected a material that is:
For the layers 12 and 16 of dielectric can be used conventional materials used for the isolation of conductors from each other and from underlying conductive elements, a suitable dielectric being, for instance silicon dioxide (“oxide”, doped or undoped) or silicon nitride (“nitride”), silicon oxynitride, fluoropolymer, parylene, polyimide, tetra-ethyl-ortho-silicate (TEOS) based oxides, boro-phosphate-silicate-glass (BPSG), phospho-silicate-glass (PSG), boro-silicate-glass (BSG), oxide-nitride-oxide (ONO), plasma enhanced silicon nitride (PSiNx), oxynitride. A low dielectric constant material, such as hydrogen silsesquioxane. HDP-FSG (high-density-plasma fluorine-doped silicate glass) is a dielectric that has a lower dielectric constant than regular oxide.
The most commonly used and therefore the preferred dielectrics of layers 12 and 16 are silicon dioxide (doped or undoped), silicon oxynitride, parylene or polyimide, spin-on-glass, plasma oxide or LPCVD oxide.
The same materials that have been highlighted above as possible materials for the layer 18 can also be considered for the layer 15 of barrier material. Barrier layer 15 is preferably about 100 and 500 Angstrom thick and more preferably about 300 Angstrom thick. Layer 18 of barrier material is preferably deposited to a thickness between about 50 and 150 Angstrom, filling recess 19, having a height between about 30 and 80 Angstrom, with the deposited barrier material.
Processes and processing conditions that are required for the creation of the structure that is shown in cross section in
As an example of the creation of layer 18 of barrier material can be cited depositing titanium silicon nitride using PECVD in a temperature range of between 200 and 500 degrees C. to a thickness of between about 20 and 400 Angstrom. Preferably, the thickness of the barrier layer 18 is less than about 200 Angstrom.
For layer 14 of etch stop material can be selected a material that comprises a silicon component, for instance dielectrics such as silicon dioxide (“oxide”, doped or undoped) or silicon nitride (“nitride”), silicon oxynitride, silicon carbide (SiC), silicon oxycarbide (SiOC) and silicon nitro carbide (SiNC).
Layer 14 is preferably deposited using methods of LPCVD or PECVD or HDCVD or sputtering or High Density Plasma CVD (HDPCVD), deposited to a thickness between about 100 and 500 Angstrom.
After the structure that is shown in cross section in
The layer 18 of barrier material,
In the cross section that is shown in
The concept of the invention, which has been highlighted using the cross sections of
It must first be noted in the cross section that is shown in
This concept of creating the layer 18, as shown in cross section of
The invention now proceeds with,
Key and of significant importance to the invention is, that during the deposition of the above highlighted layers of semiconductor material over the surface of the second layer 16 of dielectric, no copper surface is exposed and the created copper interconnects 13 therefore do not suffer any negative impact due to interaction with elements that are present in the processing environment.
Methods and processing conditions that are applied for the creation of the cross section that is shown in
By now etching openings 29.
As part of the pattern transfer through the second layer 23 of etch stop material, the layer-18 of barrier material may also be affected, resulting in back-sputtering of the barrier material of layer 18. The in this manner back-sputtered barrier material (not shown in
This deposition of barrier material over the above highlighted surface areas of openings 31 results in improved adhesion of the thereover deposited metal that is deposited to fill openings 31, facilitating this process of metal deposition.
In addition, the removal of the back-sputtered material from the surface of layers 18 reduces the thickness of these layers and as a consequence reduces the contribution of the barrier layer to the contact resistance of the contact interconnects created in openings 31, thereby reducing the contact resistance of the conductive interconnects created in openings 31.
The latter effects of reducing contact resistance of the contact interconnects and of improving metal adhesion to the sidewalls of openings 31 can be provided or enhanced by ion bombardment of the surface of the exposed layer 18 of barrier material. As an example of this latter process can be cited using Ar as sputtering ions at a temperature of about 25 to 150 degrees C. and a pressure of about 100′ to 150 mTorr for a time duration of about 5 to 10 seconds, the sputter process being time controlled.
The cross section that is shown in
It must be pointed out, relating to the cross section that is shown in
The summarize the invention:
Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications which fall within the scope of the appended claims and equivalents thereof.
Number | Date | Country | |
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Parent | 10238767 | Sep 2002 | US |
Child | 11119274 | Apr 2005 | US |