Claims
- 1. a barrier stack comprising:
a first barrier layer, the first barrier layer comprises a conductive barrier layer; and a second barrier layer above the first barrier layer, the second barrier layer comprises a conductive oxide to enhance the barrier properties of the barrier stack.
- 2. The barrier stack of claim 1 serves as a barrier for capacitor over plug structure of a memory cell.
- 3. The barrier stack of claim 2 wherein the capacitor over plug structure includes a plug having a step over an ILD layer.
- 4. The barrier stack of claim 2 further comprises a plurality of memory cells arranged in a series architecture.
- 5. The barrier stack of claim 4 wherein the capacitor over plug structure includes a plug having a step over an ILD layer.
- 6. The barrier stack of claim 1 serves as a barrier for capacitor over plug structure of a ferroelectric memory cell.
- 7. The barrier stack of claim 6 wherein the capacitor over plug structure includes a plug having a step over an ILD layer.
- 8. The barrier stack of claim 6 further comprises a plurality of memory cells arranged in a series architecture.
- 9. The barrier stack of claim 8 wherein the capacitor over plug structure includes a plug having a step over an ILD layer.
- 10. The barrier stack of claim 1 wherein the first barrier layer comprises first and second conductive sub-barrier layers, wherein an RTO is performed between the formation of the first and second sub-barrier layers.
- 11. The barrier stack of claim 10 wherein the sub-barrier layers comprises Ir, Ru, Rh, Pd, Hf or a combination thereof.
- 12. The barrier stack of claim 11 wherein the second barrier layer comprises oxides of Ir, Ru, Rh, Pd, Hf or a combination thereof.
- 13. The barrier stack of claim 10 wherein the second barrier layer comprises oxides of Ir, Ru, Rh, Pd, Hf or a combination thereof.
- 14. The barrier stack of claim 10 wherein an RTO is performed after the first barrier layer is formed and before the second barrier layer is formed.
- 15. The barrier stack of claim 14 wherein the sub-barrier layers comprises Ir, Ru, Rh, Pd, Hf or a combination thereof.
- 16. The barrier stack of claim 15 wherein the second barrier layer comprises oxides of Ir, Ru, Rh, Pd, Hf or a combination thereof.
- 17. The barrier stack of claim 14 wherein the second barrier layer comprises oxides of Ir, Ru, Rh, Pd, Hf or a combination thereof.
- 18. The barrier stack of claim 1 wherein an RTO is performed after the first barrier layer is formed and before the second barrier layer is formed.
- 19. The barrier stack of claim 18 wherein the first barrier layers comprises Ir, Ru, Rh, Pd, Hf or a combination thereof.
- 20. The barrier stack of claim 19 wherein the second barrier layer comprises oxides of Ir, Ru, Rh, Pd, Hf or a combination thereof.
- 21. The barrier stack of claim 18 wherein the second barrier layer comprises oxides of Ir, Ru, Rh, Pd, Hf or a combination thereof.
- 22. A method for forming a capacitor over plug structure comprising:
providing a substrate on which an ILD layer is formed and a plug formed on the ILD; forming a barrier stack over the ILD in contact with the plug, the barrier stack includes first and second barrier layers, the first barrier layer comprises a conductive barrier layer and the second barrier layer above the first barrier layer comprises a conductive oxide to enhance the barrier properties of the barrier stack; and forming a capacitor over the barrier layer.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part of patent application entitled “Barrier Stack with Improved Barrier Properties”, U.S. Ser. No. 10/050,246, (attorney docket number: 2002P00289US) which is herein incorporated by reference for all purposes.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
10050246 |
Jan 2002 |
US |
Child |
10604323 |
Jul 2003 |
US |