Patent Application
20230298950
This description relates to semiconductor devices and, more particularly, to detection of bond wire loss in semiconductor devices and associated redundancy mechanisms.
Semiconductor devices, such as integrated circuit devices (ICs), can be susceptible to various failure mechanisms. For instance, bond wire loss, or bond wire failure is a predominant failure mechanism for ICs that are included in a package with bond wires connecting pins (e.g., signal pins, power supply pins, etc.) with bond pads included on a corresponding IC. In some applications, such as automotive applications, devices and systems that implement and/or affect safety functions of a vehicle can be required to meet functional safety standard requirements, where those requirements can vary based on an assigned risk level. For instance, in automotive systems, automotive safety integrity level standards (ASILs) may apply that, based on risk level, require a percentage of all potential faults, which can be referred to as single point failure metrics (SPFMs), to be covered by a safety a mechanism (e.g., a detection mechanism and/or redundancy mechanism), or shown to not impact safe operation of an associated system. These percentages can be, for example, ninety percent for medium risk functions (e.g., light sensor, rain sensor), ninety-seven percent for high risk functions (e.g., unable to deploy air bag, loss of anti-lock braking), and ninety-nine percent for extremely high risk functions (e.g., prevention of unwanted air bag deployment, loss of braking).
In some aspects, the techniques described herein relate to a semiconductor device including: a package including a plurality of pins; a semiconductor die including: a first bond pad; a second bond pad; and a pass transistor having: a drain terminal electrically coupled with the first bond pad; and a source terminal electrically coupled with the second bond pad; a first bond wire extending between a pin of the plurality of pins and the first bond pad; and a second bond wire extending between the pin and the second bond pad, the pass transistor being configured to facilitate detection of at least one of: lack of electrical continuity between the pin and the first bond pad; or lack of electrical continuity between the pin and the second bond pad.
In some aspects, the techniques described herein relate to a semiconductor device, wherein: detecting the lack of electrical continuity between the pin and the first bond pad includes detecting a positive voltage shift between the first bond pad and the second bond pad; and detecting the lack of electrical continuity between the pin and the second bond pad includes detecting a negative voltage shift between the first bond pad and the second bond pad.
In some aspects, the techniques described herein relate to a semiconductor device, wherein the semiconductor die further includes a bond wire loss detection circuit operationally coupled with the first bond pad and operationally coupled with the second bond pad, the bond wire loss detection circuit being configured to detect a voltage differential between the first bond pad and the second bond pad.
In some aspects, the techniques described herein relate to a semiconductor device, wherein: the bond wire loss detection circuit is further operationally coupled with a gate terminal of the pass transistor; and the bond wire loss detection circuit is further configured, in response to the detected voltage differential exceeding a threshold, to activate the pass transistor, such that the pass transistor provides a conductive path between the first bond pad and the second bond pad.
In some aspects, the techniques described herein relate to a semiconductor device, wherein the semiconductor die further includes a latch operationally coupled between the bond wire loss detection circuit and a gate terminal of the pass transistor, the bond wire loss detection circuit being further configured, in response to the detected voltage differential exceeding a threshold, to set the latch, and the latch being configured, when set, to activate the pass transistor, such that the pass transistor provides a conductive path between the first bond pad and the second bond pad.
In some aspects, the techniques described herein relate to a semiconductor device, wherein: the latch is a set-reset latch, the set-reset latch being configured, when reset, to deactivate the pass transistor.
In some aspects, the techniques described herein relate to a semiconductor device, further including at least one functional block configured to release a reset signal of the set-reset latch in response to a supply voltage of the semiconductor device increasing from below a supply voltage threshold to above the supply voltage threshold.
In some aspects, the techniques described herein relate to a semiconductor device, wherein an output signal of the latch is accessible external to the semiconductor device.
In some aspects, the techniques described herein relate to a semiconductor device, wherein the pass transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor.
In some aspects, the techniques described herein relate to a semiconductor device, wherein the NMOS transistor is a native NMOS transistor.
In some aspects, the techniques described herein relate to a semiconductor device, wherein the pin is an electrical ground supply pin of the semiconductor device.
In some aspects, the techniques described herein relate to an integrated circuit including: a first bond pad coupled with a ground supply bus for the integrated circuit; a pass transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal being electrically coupled with the first bond pad; a second bond pad electrically coupled with the source terminal; a detection circuit operationally coupled with the first bond pad and the second bond pad, the detection circuit being configured to: detect a voltage differential between a voltage on the first bond pad and a voltage on the second bond pad; and if the voltage differential exceeds a threshold, provide an indication signal; and a set-reset latch configured to set an output signal in response to receiving the indication signal, the gate terminal being configured to; receive the output signal; and activate the pass transistor in response to the output signal being set, such that the pass transistor provides a conductive path between the first bond pad and the second bond pad.
In some aspects, the techniques described herein relate to an integrated circuit, further including at least one functional block configured to release a reset signal of the set-reset latch in response to a supply voltage of the semiconductor device increasing from below a supply voltage threshold to above the supply voltage threshold.
In some aspects, the techniques described herein relate to an integrated circuit, wherein an output signal of the set-reset latch is accessible external to the integrated circuit.
In some aspects, the techniques described herein relate to an integrated circuit, wherein the pass transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor.
In some aspects, the techniques described herein relate to an integrated circuit including: a first bond pad electrically coupled with a ground supply bus for the integrated circuit; a pass transistor having a drain terminal, a source terminal and a gate terminal, the drain terminal being electrically coupled with the first bond pad; a second bond pad electrically coupled with the source terminal; and a bias circuit operationally coupled with the gate terminal, the bias circuit being configured to: in a normal operation mode of the integrated circuit, activate the pass transistor; and in a test mode of the integrated, deactivate the pass transistor.
In some aspects, the techniques described herein relate to an integrated circuit, wherein the pass transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor.
In some aspects, the techniques described herein relate to an integrated circuit, wherein the NMOS transistor is a native NMOS transistor.
In some aspects, the techniques described herein relate to an integrated circuit, wherein deactivating the pass transistor includes applying a negative voltage to the gate terminal.
Like reference symbols in the various drawings indicate like and/or similar elements.
In order to best comply with safety standard requirements for packaged ICs, manufacturers may target to have one-hundred percent coverage (e.g., implement a detection and/or safety mechanism) for all potential single point faults. In some implementations, this objective can be difficult to achieve. For instance, with reference to the example of bond wire loss noted above, in a packaged IC with a limited number of pins (e.g., sixteen pins) the loss of a single bond wire connection that is not covered (e.g., detectable and/or covered by a safety mechanism) would result in failure to meet the high risk and extremely high risk ASIL requirements discussed above. That is, for a device with sixteen pins that are safety related, compliance with the functional safety standard (having fault coverage) for only fifteen of the sixteen pins would result in approximately ninety-three percent coverage for bond wire loss single-point faults, which will negatively influence the overall SPFMs(single point failure metrics), since ninety-three percent for package fault coverage is below the ninety-seven and ninety-nine percent requirements for high risk and extremely high risk safety functions.
Current approaches to reduce the probability of a functional fault due to bond wire loss may not achieve compliance with functional safety standards. For instance, use of multiple parallel connected bond wires to connect a package pin with a corresponding bond pad on an IC can reduce the probability of a resultant functional failure of the IC (e.g., due to loss of all bond wires). However, in the case of multiple parallel connected bond wires, detection of the failure of a single bond wire cannot be accurately detected during testing of the associated device (e.g., due to variation of bond wire resistance in combination with test equipment accuracy). Accordingly, such a single point fault (loss of a single bond wire) would be considered to not be covered during production testing and, as such, multiple parallel connected bond wires is not a solution.
This disclosure relates to approaches for detecting single point bond wire loss failures. The approaches described herein allow for compliance with safety functional standards (e.g., for automotive applications) for bond wire loss failure mechanisms. For instance, the approaches described herein allow for detection of bond wire losses during testing of an integrated circuit (e.g., prior to shipment to a customer and inclusion in a system implementing a safety function). This disclosure relates to implementations of safety mechanisms that provide for redundancy in the event of a single-point bond wire loss failure of an integrated circuit, e.g., during operation in the field. For instance, the disclosed approaches can detect and provide an indication of a bond wire loss. That indication can be accessible external to the corresponding integrated circuit, and can be used to initiate a safe operating state. In automotive applications, a safe operating state, depending on the particular safety function affected, can include providing an error indication, activating a redundant system or function, disabling one or more systems in a corresponding vehicle, etc. The particular details of a safe operating state will depend on the particular implementation (e.g., safety system)
While the approaches described herein are discussed with reference to automotive functional safety standards, the described techniques can be used in other applications, such as industrial applications, consumer electronics applications, etc. to provide for fault detection and/or to provide safety mechanisms. Further, while the approaches described herein are discussed with reference to detection of bond wire loss associated with ground supply pins for an integrated circuit, the disclosed techniques can be used to detect bond wire loss associated with other integrated circuit package pins, such as signal pins (e.g., input/output pins).
The semiconductor device 100 also includes a bond wire 112, and a bond wire 114. The bond wire 112 extends between (e.g., electrically couples) pin 106 and a bond pad 116, while the bond wire 114 extends between (e.g., electrically couples) pin 106 and a bond pad 120. In this example, the bond pad 116 is electrically coupled with a ground supply bus 118 of the IC, while the bond pad 120 is used to provide a sense signal for bond wire loss detection in the semiconductor device 100.
As shown in
In example implementations, the bond wire loss detection circuit 124 can be configured to detect a voltage difference between a voltage on the bond pad 116 and a voltage on the bond pad 120, where a voltage difference that is greater than a threshold voltage (e.g., ±350 millivolts) can indicate lack, or loss of electrical continuity between the pin 106 and the bond pad 116, or lack, or loss of electrical continuity between the pin 106 and the bond pad 120 (e.g., bond wire loss or failure).
In the semiconductor device 100, the pass transistor 122 and the bond wire loss detection circuit 124 act as a feedback system. In this example, the pass transistor 122 can be an n-channel metal-oxide-semiconductor (NMOS) transistor, with its source terminal electrically coupled with the bond pad 120 and its drain terminal electrically coupled with the bond pad 116. In other implementations, other transistors, devices or gates can be used as a pass device.
In the example of
Such an approach provides a redundant safety mechanism for providing an electrical ground reference for operation of the IC of the semiconductor device 100. For instance, if the bond wire 112 were to fail, the one or more IC functional blocks 126 would become inoperable, as they would no longer have an electrical ground supply reference provided on the ground supply bus 118. The redundant mechanism the bond wire loss detection circuit 124 activating the pass transistor 122 allows for the IC of the semiconductor device 100 to remain functional in the event of loss of the bond wire 112 (of loss of the bond wire 114).
In some implementations, the bond wire loss detection circuit 124 can include test circuitry that allows operating the bond wire loss detection circuit 124 to confirm its proper operation. For instance, in an example implementation, the bond wire loss detection circuit 124 can include an additional input terminal, which, in a test mode, could be connected to a test pin of the IC and the test pin connected to an external voltage source. The voltage source could then be swept (e.g., from −400 mV to +400 mV) such that a positive threshold and a negative threshold of the bond wire loss detector can be measured. In a normal operation mode of the IC, this additional input terminal would not be used (e.g., could be connected, via a transistor, to one of the two functional inputs). An example of such an approach is further illustrated in
As shown in
The set-reset latch 228, when reset, deactivates the pass transistor 222 (e.g., places the pass transistor 222 in a non-conductive state). If the bond wire 212 and the bond wire 214 are intact and properly connected in the semiconductor device 200, the bond wire loss detection circuit 224 will not detect a voltage difference between the bond pad 216 and the bond pad 220, the set-reset latch 228 will remain unset (e.g., ready to be SET), and the pass transistor 222 will remain deactivated.
Additionally, in example implementations, the set-reset latch 228 of the semiconductor device 200 can prevent oscillation of its bond wire loss detection feedback loop. In other implementations, such as the example, of
Referring again to
As shown in
However, in this example, elements of the bond wire loss feedback circuit 400 shown in
In some implementations of the bond wire loss feedback circuit 400, anti-parallel diodes can be coupled between the bond pad 416 and the bond pad 420, where the anti-parallel diodes can be configured to limit voltage excursions on the bond pad 416 and/or the bond pad 420 when the bond wire 412 and/or the bond wire 414 is disconnected (lost) before the pass transistor 422 is activated. In some implementations, such anti-parallel diodes can be implemented by electrostatic discharge protection diodes (not depicted in
As shown in
In the example of
In the bond wire loss feedback circuit 400 of the
As indicated above, in normal operation mode of the bond wire loss feedback circuit 400, the detector 460a operates with the branch B2 including the PMOS transistor 524, the node 590a, the NMOS transistor 526, and the resistor 528, while in the test mode of the bond wire loss feedback circuit 400, the detector 460a operates with the branch B2 including the PMOS transistor 525, the node 590b, the NMOS transistor 527, and the resistor 529, and the resistor 529. As shown in
In the bond wire loss feedback circuit 400, when the bond wire 412 and the bond wire 414 are connected as intended (e.g., providing electrical continuity from their respective bond pads to the pin 406), respective voltage potentials on the bond pad 416 and the bond pad 420 will be the same (approximately the same, nearly the same). In this situation, a gate-to-source voltage of a NMOS transistor 521 will be equal to a sum of a gate-to-source voltage of the NMOS transistor 526 and a voltage across the resistor 528 (and also equal to a sum of a gate-source voltage of the NMOS transistor 527 and a voltage across the resistor 529 for test mode). In other words, the gate-to-source voltage of the NMOS transistor 521 will be larger than a gate-to-source voltage of the NMOS transistor 526 and the 527, which will cause respective currents in the NMOS transistor 526 and the NMOS transistor 527 to be smaller than a current it the NMOS transistor 521. Since currents in the PMOS transistor 524 and the PMOS transistor 525 are approximately the same as a current in the NMOS transistor 521, a voltage on the node 590a (normal operation) or the node 590b (test mode) will be pulled towards the supply voltage, which will deactivate the 522 (normal operation) or the PMOS transistor 523, which will result in node 425b being grounded.
If, however, electrical continuity between, e.g., the bond wire 412 and the bond pad 416 is lost, or not present, a voltage on the bond pad 416 will increase, which will cause a gate voltage of the NMOS transistor 526 (normal operation) of the NMOS transistor 527 (test mode) to increase. Once the gate-to-source voltage of the NMOS transistor 526 (in normal operation), or the gate-to-source voltage of the NMOS transistor 527 becomes larger than a gate-to-source voltage of the 521, that increase voltage will provide more current than the PMOS transistor 524 (normal operation), or the PMOS transistor 525, such that the node 590a (normal operation), or the node 590b (test mode) will be pulled to ground and a resulting voltage on the node 425b will cause OR gate 425 to set the set-reset latch 428. The bond wire loss detector 460b, in response to loss of the bond wire 414, will operate similarly to the bond wire loss detector 460a, in response to loss of the bond wire 412. Accordingly, for purposes of brevity, details of operation of the bond wire loss detector 460b are not described here.
In the bond wire loss feedback circuit 400, when a TM_en control signal (indicated in
When the bond wire loss feedback circuit 400 is put in its test mode (e.g., TM_en and HiZ pulled high), an external test voltage can be sourced on pin 436. This test voltage can be swept, as noted above, from −550 mV to +550 mV to determine the threshold voltages of the bond wire loss detector 460a and the bond wire loss detector 460b, and to confirm proper operation of the bond wire loss detector 424.
The indication portion 424b of the bond wire loss detection circuit 424 includes the OR gate 425 that receives inputs that respectively indicated detection of a positive voltage differential with a magnitude greater than a threshold voltage (input 425a) on bond pad 420 (normal operation) or node 800 (test mode) referenced to bond pad 416, and detection of a negative voltage differential with a magnitude greater than the threshold voltage (input 425b). If either of such voltage differentials is detected, the OR gate 425 will output a logic one (logic high), setting the set-reset latch 428 and activating the pass transistor 422. As further shown in
The various apparatus and techniques described herein may be implemented using various semiconductor processing and/or packaging techniques. Some embodiments may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Silicon Carbide (SiC), and/or so forth.
It will also be understood that when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present.
Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.
As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.
While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The embodiments described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different embodiments described.
