Claims
- 1. A process for preparing a semiconductor light emitting element comprising:a step of forming a first epitaxial growth layer comprising a laminate where a first cladding layer, an active layer, and a second cladding layer are deposited in turn on a first semiconductor substrate by growing mixed crystals of a compound semiconductor, a step of forming a cover layer on said first epitaxial growth layer, a step of exposing a surface of said first epitaxial growth layer by removing said cover layer, a step of integrally joining a second semiconductor substrate having a mirror-finished main surface to said first epitaxial growth layer having the exposed surface by placing the substrate on said first epitaxial growth layer so that said main surface of the substrate may come into contact with said first epitaxial growth layer, a step of subjecting the laminate to a heat treatment at a temperature below a temperature at which the bonding surface is broken owing to a difference between thermal expansion coefficients of said first semiconductor substrate and said second semiconductor substrate, a step of exposing said first epitaxial growth layer by removing said first semiconductor substrate, and a step of forming electrodes on the front side of said first epitaxial growth layer and on the back side of said second semiconductor substrate.
- 2. The process for preparing the semiconductor light emitting element according to claim 1, wherein said first cladding layer is formed by selecting a composition ratio of said mixed crystals so that a lattice constant of the cladding layer may match a lattice constant of said first semiconductor substrate,said first semiconductor substrate is formed from GaAs, said first laminate is a compound semiconductor layer represented by the formula Inx(Ga1−yAly)1−xP, a composition ratio of said first cladding layer in said formula is 0.45<x<0.50 and 0≦y≦1, and said second semiconductor substrate is formed from GaP.
- 3. The process for preparing the semiconductor light emitting element according to claim 1 further comprising the step of partially removing said active layer to thereby make an area of said active layer on said second semiconductor substrate smaller than an area of said second semiconductor substrate.
Priority Claims (3)
Number |
Date |
Country |
Kind |
11-162985 |
Jun 1999 |
JP |
|
11-174138 |
Jun 1999 |
JP |
|
2000-089754 |
Mar 2000 |
JP |
|
Parent Case Info
This application is a Div of Ser. No. 09/589,452 Jun. 08, 2000 U.S. Pat. No. 6,465,809.
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