Patent Application
20190369706
Portable communication devices (e.g., cellular telephones, smart phones, tablet computers, portable game consoles, wearable devices, and other battery-powered devices) and other computing devices continue to offer an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, such devices have become more powerful and more complex. Portable communication devices now commonly include a system on chip (SoC) comprising a plurality of processing devices embedded on a single substrate, which may read data from and store data in an external system memory comprising volatile memory (e.g., double data rate (DDR) dynamic random access memory (DRAM)) via a high-speed bus.
The SoC processing devices may comprise one or more central processing units (CPUs), a wireless communication processor (e.g., a modem processor), and a dynamic clock and voltage scaling (DCVS) controller. The modem processor is configured to manage data communications with a wireless wide area network (WWAN) supporting various wireless technologies (fourth generation (“4G”), fifth generation (“5G”), etc.). The DCVS controller is configured to selectively adjust the frequency and/or voltage applied to the SoC processing components to yield a desired performance and/or power efficiency characteristics.
In conventional wireless data communication solutions, the frequency of the CPUs may be adjusted in a step-wise fashion while load is evaluated at a predetermined sampling interval (e.g., every few msec). However, because WWAN download data is inherently bursty, it is difficult for the CPU and DVCS controller/scheduler to react quickly enough to adjust to the new workload. This delayed reaction time to the increased workload frequently results in packets getting dropped and can result in higher latency times, which ultimately translate to poor user experience. This problem will only get worse with the adoption and advancement of wireless standards (e.g., 5G) where the data rates are significantly higher and there is a need for very low latency and high reliability requirements. Furthermore, not processing WWAN workloads with the optimal frequency may also result in using the CPU core for longer durations, which can result in more power consumption.
Accordingly, there is a need for improved systems and methods for processing wireless download data in a portable communication device.
Systems, methods, and computer programs are disclosed for processing wireless download data in a portable communication device. An embodiment of a method comprises a wireless communication processor receiving incoming packet data via a wireless communication network. The wireless communication processor generates and inserts burst metadata into a burst of packets comprising a portion of the incoming packet data. The burst metadata specifies one or more workload parameters associated with the burst of packets. The wireless communication processor transmits the burst metadata and the burst of packets to a central processing unit (CPU). The CPU initiates an adjustment of an operating parameter for processing the burst of packets in accordance with the one or more workload parameters in the burst metadata.
An embodiment of a system for processing wireless download data in a portable communication device comprises a central processing unit (CPU), a wireless communication processor, and a dynamic clock and voltage scaling (DCVS) controller electrically coupled via a system bus. The wireless communication processor is configured to: receive incoming packet data via a wireless communication network; generate and insert burst metadata into a burst of packets comprising a portion of the incoming packet data that specifies one or more workload parameters associated with the burst of packets; and transmit the burst metadata and the burst of packets to the CPU. The DCVS controller is configured to adjust a frequency of the CPU for processing the burst of packets in accordance with the one or more workload parameters in the burst metadata.
In the Figures, like reference numerals refer to like parts throughout the various views unless otherwise indicated. For reference numerals with letter character designations such as “102A” or “102B”, the letter character designations may differentiate two like parts or elements present in the same Figure. Letter character designations for reference numerals may be omitted when it is intended that a reference numeral to encompass all parts having the same reference numeral in all Figures.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
In this description, the term “application” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, an “application” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
The term “content” may also include files having executable content, such as: object code, scripts, byte code, markup language files, and patches. In addition, “content” referred to herein, may also include files that are not executable in nature, such as documents that may need to be opened or other data files that need to be accessed.
As used in this description, the terms “component,” “database,” “module,” “system,” and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device may be a component. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components may execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).
In this description, the terms “communication device,” “wireless device,” “wireless telephone”, “wireless communication device,” and “wireless handset” are used interchangeably. With the advent of third generation (“3G”), fourth generation (“4G”), fifth generation (“5G”) and other wireless technology, greater bandwidth availability has enabled more portable computing devices with a greater variety of wireless capabilities.
As illustrated in
Wireless communication processor 114 is configured to manage communications with one or more wireless networks, including, for example, a wireless wide area network (WWAN) and/or a wireless local area network (WLAN). As known in the art, WWAN may support various wireless technology (e.g., third generation (“3G”), fourth generation (“4G”), fifth generation (“5G”), and other wireless technology). In an embodiment, wireless communication processor 114 comprises a modem processor.
Power controller 124 is electrically coupled to a power supply 106 via a power control bus, which comprises a power monitor 132 configured to measure energy usage associated with the SoC 102 and the DRAM 104 and, thereby, monitor device power consumption.
DCVS controller 118 is configured to implement various DCVS techniques. As known in the art, the DCVS techniques involve selectively adjusting the frequency and/or voltage applied to the SoC components (e.g., CPU 108, power controller 124, DRAM controller 122, cache controller 120, and other hardware devices) to yield desired performance and/or power efficiency characteristics.
DRAM controller 122 is configured to manage communication between SoC 102 and DRAM 104, including read and/or write transactions from memory clients residing on SoC 102.
Cache controller 120 is configured to manage a system cache 122, which stores data so future requests for data may be served faster. In an embodiment, cache 122 may comprise a multi-level hierarchy (e.g., level one (L1) cache, level two (L2) cache, etc.) with a “last level” (L3) cache that may be shared among the SoC processing devices.
Referring to
As illustrated in
In connection with the incoming download packet data 204, wireless communication processor 114 generally performs certain dedicated packet management functions via burst-responsive packet management module 113, and CPU 108 generally schedules and processes the workload generated by the incoming download packet data 204 as they are received from wireless communication processor 114. In other words, as known in the art, wireless communication processor 114 performs “packet processing” whereas CPU 108 performs “workload processing”. In general, burst-responsive packet manager module 113 in wireless communication processor 114 processes incoming packets from various services and, prior to transmitting to CPU 108, generates and inserts burst metadata into a packet burst 209 comprising a portion of the incoming packet data 204. As described below in more detail, the burst metadata may specify one or more workload parameters associated with the packet burst 209, which may be transmitted with the packet data to CPU 108. Workload scheduler 109 interprets the burst metadata to evaluate a current workload and, in response, take steps to address an upcoming increase in workload by, for example, adjusting one or more operating parameters for processing the packet burst 209.
During a wireless download, the rate of packets (i.e., packets/msec) at wireless communication processor 114 can vary significantly, resulting in packet burst(s) 209 that can lead to undesirable results, such as, dropped packets, increased workload latency, and power inefficiencies. For example, in conventional wireless device architectures, the frequency of the CPU(s) used to handle the workload generated by incoming download packet data may be adjusted in a step-wise fashion while the load is evaluated at a predetermined sampling interval (e.g., every few msec). Because wireless download data is inherently bursty, the sampling interval of the CPU and DCVS controller/scheduler may be insufficient to react quickly enough to adjust to new workload. This delayed reaction time to exponentially increased workload generated by incoming download packet data may result in packets getting dropped and can result in higher latency times, which ultimately translate to poor user experience. This problem will only get worse with the adoption and advancement of wireless standards (e.g., 5G) where the data rates are significantly higher and there is a need to meet very low latency and high reliability requirements. Furthermore, not processing workloads with the optimal frequency may also result in using the core for longer durations, which can result in more power consumption.
In this manner, burst-responsive download packet manager module 113 may determine, as incoming packets are received, when a packet burst scenario (i.e., packet burst 209) is likely or has occurred, which may lead to dropped packets, increased workload latency, and/or power inefficiencies based on a current workload operating parameter. The current workload operating parameter may involve any of the following, or other parameters: a current CPU frequency, a current DDR frequency, a cache frequency, a current DCVS voltage/frequency setting, a cache state, etc.).
Regardless of the workload characteristics and/or specific threshold values, in response to a packet burst scenario, burst-responsive download packet manager module 113 may perform certain specialized packet management functions before transmitting the IP packet data to CPU 108 for workload scheduling and processing. As illustrated in
Regardless the particular content and/or format of the burst metadata, the information/data marker 208 (i.e., the burst metadata) and the IP packet data 210 associated with packet burst 209 are transmitted to CPU 108. In one embodiment, the information/data marker 208 is transmitted in a packet header with IP packet data 210 via an in-band channel 214. It should be appreciated, however, that the burst metadata may also be separately transmitted to CPU 108 via the in-band channel 214 or via a separate out-of-band channel 216.
As further illustrated in
For purposes of illustrating remedial adjustment of the CPU frequency in response to the burst metadata, the graph 500 in
Another example of the benefits of remedial adjustment of the CPU frequency in response to the burst metadata is illustrated in
As further illustrated in
As illustrated at reference numeral 226, another workload adjustment may involve reducing the frequency of a DDR bus electrically coupling the DRAM 104 to DRAM controller 122. Yet another workload adjustment may involve adjusting the state and/or performance of the cache 122 (reference numeral 222). As known in the art, a last-level (L3) cache can significantly improve performance. L3 cache may be power collapsed whenever CPU 108 is in a power-saving mode. In response to the packet burst scenario and receiving information/data marker 208, cache controller 120 may wake-up the L3 cache, which may reduce the additional latency/delay of waking up L3 cache from the cold when a burst of packets are received from wireless communication processor 113. In this regard, information/data marker 208 may also provide, for example, burst metadata related to incoming packet load details that may allow CPU 108 (or cache controller 120) to configure the L3 cache frequency to meet workload demand.
As mentioned above, the system 100 may be incorporated into any desirable computing system.
A display controller 728 and a touch screen controller 730 may be coupled to the CPU 702. In turn, the touch screen display 706 external to the on-chip system 722 may be coupled to the display controller 828 and the touch screen controller 730.
Further, as shown in
A stereo audio coder-decoder (CODEC) 750 may be coupled to the multicore CPU 702. Moreover, an audio amplifier 752 may be coupled to the stereo audio CODEC 750. In an exemplary aspect, a first stereo speaker 754 and a second stereo speaker 756 are coupled to the audio amplifier 752.
As depicted in
It should be appreciated that one or more of the method steps described herein may be stored in the memory as computer program instructions, such as the modules described above. These instructions may be executed by any suitable processor in combination or in concert with the corresponding module to perform the methods described herein.
Certain steps in the processes or process flows described in this specification naturally precede others for the invention to function as described. However, the invention is not limited to the order of the steps described if such order or sequence does not alter the functionality of the invention. That is, it is recognized that some steps may performed before, after, or parallel (substantially simultaneously with) other steps without departing from the scope and spirit of the invention. In some instances, certain steps may be omitted or not performed without departing from the invention. Further, words such as “thereafter”, “then”, “next”, etc. are not intended to limit the order of the steps. These words are simply used to guide the reader through the description of the exemplary method.
Additionally, one of ordinary skill in programming is able to write computer code or identify appropriate hardware and/or circuits to implement the disclosed invention without difficulty based on the flow charts and associated description in this specification, for example.
Therefore, disclosure of a particular set of program code instructions or detailed hardware devices is not considered necessary for an adequate understanding of how to make and use the invention. The inventive functionality of the claimed computer implemented processes is explained in more detail in the above description and in conjunction with the Figures which may illustrate various process flows.
In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, NAND flash, NOR flash, M-RAM, P-RAM, R-RAM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer.
Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (“DSL”), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.
Disk and disc, as used herein, includes compact disc (“CD”), laser disc, optical disc, digital versatile disc (“DVD”), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
Alternative embodiments will become apparent to one of ordinary skill in the art to which the invention pertains without departing from its spirit and scope. Therefore, although selected aspects have been illustrated and described in detail, it will be understood that various substitutions and alterations may be made therein without departing from the spirit and scope of the present invention, as defined by the following claims.
